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| S1X60000 series design guide design guide S1X60000 series design guide embedded array S1X60000 series epson electronic devices website electronic devices marketing division http://www.epsondevice.com document code: 404624401 first issue september, 2004 printed in japan c b this manual was made with recycle papaer, and printed using soy-based inks.
notice no part of this material may be reproduced or duplicated in any form or by any means without the written permission of seiko epson. seiko epson reserves the right to make changes to this material without notice. seiko epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as medical products. moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. this material or portions thereof may contain technology or the subject relating to strategic products under the control of the foreign exchange and foreign trade law of japan and may require an export license from the ministry of international trade and industry or other approval from another government agency. ms-dos and windows are registered trademarks of microsoft corporation, u.s.a. pc/at, ps/2, pc-dos, vga, ega and ibm are registered trademarks of international business machines corporation, u.s.a. verilog-xl is a registered trademark of cadence design systems corporation, u.s.a. vss is a registered trademark of synopsys of inc., u.s.a. modelsim is a registered trademark of model technology corp., u.s.a. all other product names mentioned herein are trademarks and/or registered trademarks of their respective owners. ?eiko epson corporation 2004, all rights reserved. configuration of product number devices s1 x 65013 f 00a0 packing specifications ( * 3) specifications shape ( * 2) model number model name ( * 1) product classification (s1:semiconductors) 00 * 1: model name * 2: shape k standard cell l gate array x embedded array b assembled on board, cob, bga c plastic dip d bare chip f plastic qfp h ceramic dip l ceramic qfp m plastic sop r tab?fp t tape carrier (tab) 2 tsop (standard bent) 3 tsop (reverse bent) ? 3: packing specifications 14th packing specifications 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 15th 0 a b c d e f g h j k l m n p q r 9 besides tape & reel tcp bl 2 directions tape & reel back tcp br 2 directions tcp bt 2 directions tcp bd 2 directions tape & reel front tcp bt 4 directions tcp bd 4 directions tcp sl 2 directions tcp sr 2 directions tape & reel left tcp st 2 directions tcp sd 2 directions tcp st 4 directions tcp sd 4 directions tape & reel right specs not fixed table of contents embedded array S1X60000 series epson i design guide S1X60000 series table of contents chapter 1 overview ............................................................................. 1 1.1 features....................................................................................................................... ............ 1 1.1.1 outline of the S1X60000 series ................................................................................1 1.1.2 internal structure of the S1X60000 series ..............................................................3 1.1.3 structure and types of msis.....................................................................................3 1.1.4 structure of 5 v tolerant fail-safe cells .................................................................3 1.1.5 structure and types of input/output buffers..........................................................3 1.2 electrical characteristics and specifications ....................................................................... 4 1.2.1 when using standard type input/output buffers (x type) ...................................4 1.2.2 when using 5 v tolerant fail-safe input/output buffers (xf type) .................10 1.3 estimating the quiescent current ...................................................................................... 16 1.3.1 quiescent current in the random logic part (i qbc ) .............................................16 1.3.2 quiescent current of basic cell type ram (i qbm ) ................................................16 1.3.3 quiescent current of input/output buffers (i qio ) .................................................17 1.3.4 temperature characteristics of quiescent current ..............................................19 1.4 embedded array development flow................................................................................... 20 chapter 2 estimating the gate density............................................ 22 2.1 dividing up logic between chips....................................................................................... 22 2.2 estimating the gate counts used....................................................................................... 22 2.3 estimating the number of input/output pins ................................................................... 22 2.4 bulk list...................................................................................................................... .......... 23 chapter 3 msi cells........................................................................... 24 3.1 msi cell types................................................................................................................. ..... 24 chapter 4 types of input/output buffers and their use (x type).. 27 4.1 types of input/output buffers............................................................................................. 27 4.1.1 selecting input/output buffers.................................................................................27 4.1.2 bus hold circuit.......................................................................................................28 4.2 input/output buffers for a single power supply ............................................................... 29 4.2.1 input buffers ............................................................................................................29 4.2.2 output buffers .........................................................................................................30 4.2.3 bi-directional buffers...............................................................................................32 4.2.4 fail-safe cells ..........................................................................................................34 4.2.5 gated cells ...............................................................................................................36 4.3 dual power supply input/output buffers .......................................................................... 38 4.3.1 input buffers ............................................................................................................38 4.3.2 output buffers .........................................................................................................40 4.3.3 bi-directional buffers...............................................................................................44 4.3.4 fail-safe cells ..........................................................................................................49 4.3.5 gated cells ...............................................................................................................51 4.4 dual power supplies guidelines ......................................................................................... 52 4.4.1 method of adapting to dual power supplies .........................................................52 4.4.2 power supplies for dual power operation.............................................................52 4.4.3 turning on/off dual power supplies.....................................................................52 chapter 5 types of input/output buffers and their use (xf type)........................................................................... 53 5.1 types of input/output buffers............................................................................................. 53 5.1.1 selecting input/output buffers.................................................................................53 5.1.2 bus hold circuit.......................................................................................................54 table of contents ii epson embedded array S1X60000 series design guide 5.2 dual power supply input/output buffers .......................................................................... 55 5.2.1 input buffers ........................................................................................................... 55 5.2.2 output buffers......................................................................................................... 57 5.2.3 bi-directional buffers .............................................................................................. 61 5.2.4 fail-safe cells.......................................................................................................... 66 5.2.5 gated cells............................................................................................................... 68 5.2.6 5 v tolerant fail-safe cells ................................................................................... 70 5.3 dual power supplies guidelines.......................................................................................... 73 5.3.1 method of adapting to dual power supplies......................................................... 73 5.3.2 power supplies for dual power operation ............................................................ 73 5.3.3 turning on/off dual power supplies .................................................................... 73 5.3.4 interface with external devices .............................................................................. 74 chapter 6 memory blocks.................................................................. 76 6.1 basic cell type ram (asynchronous) ................................................................................. 76 6.1.1 features ................................................................................................................... 76 6.1.2 ram word/bit configuration and simulation model selection........................... 77 6.1.3 ram size.................................................................................................................. 77 6.1.4 investigating ram placement on master slice..................................................... 79 6.1.5 explanation of functions ........................................................................................ 80 6.1.6 delay parameters .................................................................................................... 83 6.1.7 timing charts........................................................................................................ 115 6.2 basic cell type ram (synchronous type)........................................................................ 117 6.2.1 features ................................................................................................................. 117 6.2.2 word/bit configurations and cell names of the ram ....................................... 117 6.2.3 ram sizes .............................................................................................................. 118 6.2.4 investigating ram placement on master slice................................................... 118 6.2.5 functional description.......................................................................................... 119 6.2.6 timing charts........................................................................................................ 123 6.2.7 delay parameters .................................................................................................. 125 6.3 standard type 1 port ram ................................................................................................ 141 6.3.1 features ................................................................................................................. 141 6.3.2 ram sizes .............................................................................................................. 141 6.3.3 input signals and block diagrams ...................................................................... 142 6.3.4 truth table of device operation .......................................................................... 143 6.3.5 timing charts........................................................................................................ 144 6.3.6 electrical characteristics...................................................................................... 145 6.4 standard type dual port ram.......................................................................................... 147 6.4.1 features ................................................................................................................. 147 6.4.2 ram sizes .............................................................................................................. 147 6.4.3 input signals and block diagrams ...................................................................... 148 6.4.4 truth table of device operation .......................................................................... 150 6.4.5 timing charts........................................................................................................ 151 6.4.6 electrical characteristics...................................................................................... 153 6.5 high density type 1 port ram.......................................................................................... 155 6.5.1 features ................................................................................................................. 155 6.5.2 ram sizes .............................................................................................................. 155 6.5.3 input/output signals and block diagrams ......................................................... 156 6.5.4 truth table of device operation .......................................................................... 157 6.5.5 timing charts........................................................................................................ 158 6.5.6 electrical characteristics...................................................................................... 159 6.6 mask rom....................................................................................................................... .... 161 6.6.1 features ................................................................................................................. 161 6.6.2 rom sizes.............................................................................................................. 161 6.6.3 input/output signals and block diagrams ......................................................... 162 6.6.4 truth table of device operation .......................................................................... 163 6.6.5 timing charts........................................................................................................ 163 6.6.6 electrical characteristics...................................................................................... 164 table of contents embedded array S1X60000 series epson iii design guide 6.7 access to nonexistent addresses inhibited ...................................................................... 165 chapter 7 propagation delay and timing ...................................... 166 7.1 accuracy of the propagation delay time .......................................................................... 166 7.2 calculating the propagation delay time.......................................................................... 166 7.3 virtual wiring capacitance ............................................................................................... 167 7.4 fluctuations in propagation delay time .......................................................................... 170 7.5 setup and hold times of the flip-flop (ff) ..................................................................... 172 chapter 8 estimating power consumption .................................... 175 8.1 calculation of power consumption ................................................................................... 175 8.1.1 internal cells (p int ).................................................................................................175 8.1.2 input buffers (p i )....................................................................................................176 8.1.3 output buffers (p o ) ................................................................................................176 8.2 limitations on power consumption .................................................................................. 177 chapter 9 circuit design................................................................. 179 9.1 basic circuit configuration ............................................................................................... 179 9.1.1 inserting input/output buffers.............................................................................179 9.1.2 limitations on logic gate output load ...............................................................179 9.1.3 wired logic forbidden...........................................................................................179 9.1.4 synchronized design recommended ....................................................................180 9.2 use of differentiating circuits forbidden ........................................................................ 181 9.3 clock tree synthesis .......................................................................................................... 1 82 9.3.1 overview .................................................................................................................182 9.3.2 design flow ............................................................................................................183 9.3.3 applying clock tree synthesis .............................................................................184 9.3.4 limitations and notes ...........................................................................................186 9.3.5 clock tree synthesis checksheet .........................................................................187 9.3.6 attached materials.................................................................................................188 9.4 designing fast operating circuits.................................................................................... 192 9.5 metastable state............................................................................................................... .. 193 9.6 configuration of the internal bus ..................................................................................... 194 9.7 preventing contention with external buses .................................................................... 196 9.8 hazard protection.............................................................................................................. . 197 9.9 oscillation circuits ........................................................................................................... .. 198 9.9.1 configuration of oscillation circuits ....................................................................198 9.9.2 notes regarding the use of oscillation circuits .................................................200 9.10 restrictions and constraints on vhdl/verilog-hdl netlist ......................................... 201 9.10.1 common restrictions and constraints.................................................................201 9.10.2 restrictions and constraints for verilog netlist .................................................202 9.10.3 restrictions and constraints on vhdl netlist ...................................................203 9.10.4 description of oscillation cell and ac/dc test circuit cell l1tcir2 .............203 9.10.5 clock buffer description........................................................................................204 9.11 pin layout and simultaneous operation.......................................................................... 206 9.11.1 estimating the number of power supply pins ....................................................206 9.11.2 simultaneous operation and adding power supplies.........................................208 9.11.3 cautions and notes regarding the pin layout ...................................................213 9.11.4 example of the recommended pin layout...........................................................219 9.12 about power supply cutoff (x type) ................................................................................ 220 9.12.1 for single power supply systems ........................................................................220 9.12.2 for dual power supply systems...........................................................................220 9.13 about power supply cutoff (xf type) .............................................................................. 222 9.13.1 cell types usable during cut-off..........................................................................222 table of contents iv epson embedded array S1X60000 series design guide chapter 10 circuit design that takes testability into account .... 225 10.1 consideration regarding circuit initialization ................................................................ 225 10.2 consideration regarding compressing the test patterns............................................... 225 10.3 test circuit which simplifies dc and ac testing .......................................................... 225 10.3.1 configuration of test circuits.................................................................................... 226 10.4 memory block test circuits ............................................................................................... 233 10.4.1 basic cell type ram............................................................................................. 233 10.4.2 standard type 1 port ram................................................................................... 238 10.4.3 standard type dual port ram ............................................................................ 239 10.4.4 high density type ram ....................................................................................... 239 10.4.5 mask rom ............................................................................................................. 239 10.5 memory bist design.......................................................................................................... 241 10.5.1 outline of the memory bist circuit block ......................................................... 241 10.5.2 outline of the memory bist circuit test sequence........................................... 243 10.5.3 types of memory suitable for memory bist ...................................................... 243 10.5.4 estimating the memory bist circuit size.......................................................... 243 10.5.5 about memory bist circuit design .................................................................... 244 10.5.6 other ...................................................................................................................... 246 10.6 function cell test circuits ................................................................................................ 252 10.6.1 test circuit structures ......................................................................................... 252 10.6.2 test patterns ......................................................................................................... 252 10.6.3 test circuit data ................................................................................................... 253 10.7 scan design .................................................................................................................... ..... 254 10.7.1 about the scan circuit.......................................................................................... 254 10.7.2 scan design flow .................................................................................................. 255 10.7.3 design rules .......................................................................................................... 256 10.8 boundary scan design........................................................................................................ 265 10.8.1 boundary scan design flow................................................................................. 265 10.8.2 instructions............................................................................................................ 266 10.8.3 estimating the number of gates ......................................................................... 266 10.8.4 design rules .......................................................................................................... 266 chapter 11 test pattern generation............................................... 271 11.1 testability consideration ................................................................................................... 271 11.2 usable input waveforms .................................................................................................... 271 11.3 constraints on test patterns ............................................................................................. 272 11.3.1 test rate and event counts................................................................................. 272 11.3.2 input delay ............................................................................................................ 272 11.3.3 pulse width............................................................................................................ 272 11.3.4 input waveform format ....................................................................................... 272 11.3.5 strobes.................................................................................................................... 272 11.4 notes regarding dc testing.............................................................................................. 273 11.5 notes regarding the use of oscillation circuits .............................................................. 275 11.6 regarding ac testing......................................................................................................... 27 6 11.6.1 constraints regarding measurement events ..................................................... 276 11.6.2 constraints on the measurement location for ac testing................................ 276 11.6.3 constraints regarding the path delay which is tested .................................... 276 11.6.4 other constraints.................................................................................................. 276 11.7 test patterns constraints for bi-directional pins ............................................................ 277 11.8 notes on device in a high impedance state ..................................................................... 277 appendix a1 electrical characteristics data (x type)................... 278 a1.1 characteristics of input/output buffers (3.3 v operation)..................................................... 278 a1.1.1 input buffer characteristics (3.3 v 0.3 v) ........................................................ 278 a1.1.2 input through current (3.3 v 0.3 v) ................................................................ 279 a1.1.3 output buffer characteristics (3.3 v 0.3 v) ..................................................... 282 table of contents embedded array S1X60000 series epson v design guide a1.2 characteristics of input/output buffers (2.5 v operation) .................................................... 290 a1.2.1 input buffer characteristics (2.5 v 0.2 v).........................................................290 a1.2.2 input through current (2.5 v 0.2 v) .................................................................291 a1.2.3 output buffer characteristics (2.5 v 0.2 v)......................................................292 a1.3 characteristics of input/output buffers (2.0 v operation) .................................................... 299 a1.3.1 input buffer characteristics (2.0 v 0.2 v).........................................................299 a1.3.2 input through current (2.0 v 0.2 v) .................................................................300 a1.3.3 output buffer characteristics (2.0 v 0.2 v)......................................................301 appendix a2 electrical characteristics data (xf type) ................ 308 a2.1 characteristics of input/output buffers (3.3 v operation) .................................................... 308 a2.1.1 input buffer characteristics (3.3 v 0.3 v).........................................................308 a2.1.2 input through current (3.3 v 0.3 v) .................................................................309 a2.1.3 output buffer characteristics (3.3 v 0.3 v)......................................................312 a2.2 characteristics of input/output buffers (2.5 v operation) .................................................... 320 a2.2.1 input buffer characteristics (2.5 v 0.2 v).........................................................320 a2.2.2 input through current (2.5 v 0.2 v) .................................................................321 a2.2.3 output buffer characteristics (2.5 v 0.2 v)......................................................322 a2.3 characteristics of input/output buffers (2.0 v operation) .................................................... 329 a2.3.1 input buffer characteristics (2.0 v 0.2 v).........................................................329 a2.3.2 input through current (2.0 v 0.2 v) .................................................................330 a2.3.3 output buffer characteristics (2.0 v 0.2 v)......................................................331 a2.4 characteristics of input/output buffers (5 v tolerant fail-safe cell)........................... 338 a2.4.1 input buffer characteristics (3.3 v 0.3 v).........................................................338 a2.4.2 input through current (3.3 v 0.3 v) .................................................................338 a2.4.3 output buffer characteristics (3.3 v 0.3 v)......................................................339 chapter 1 overview embedded array S1X60000 series epson 1 design guide chapter 1 overview epson?s S1X60000 series consists of ultra high speed, super integrated cmos type embedded arrays manufactured by the 0.25 m process. 1.1 features 1.1.1 outline of the S1X60000 series ? integration 27.4k gates/mm 2 ? operating speed internal gates 107 ps (2.5 v, typ.), 140 ps (2.0 v, typ.) (2 input nand, f/o = 1, standard wiring load) input buffers f/o = 2, standard wiring load, typ. condition operating speed x type xf type voltage 3.3 v input buffer (xhibc) 3.3 v input buffer (xfhibc) 5 v tolerant fail-safe input buffer (xfhibb) unit 3.3 v/2.5 v 260 260 270 ps operating speed x type xf type voltage 2.5 v/2.0 v input buffer (xibc) 2.5 v/2.0 v input buffer (xflibc) 5 v tolerant fail-safe input buffer unit 2.5 v 270 270 ? ps 2.0 v 360 360 ? ps output buffers c l = 15pf, typ.condition operating speed x type xf type voltage 3.3 v output buffer (xhob3at) 3.3 v output buffer (xfhob3at) 5 v torelant fail-safe output buffer (xfhobf3at) unit 3.3 v/2.5 v 1.5 1.5 1.9 ns chapter 1 overview 2 epson embedded array S1X60000 series design guide operating speed x type xf type voltage 2.5 v/2.0 v output buffer (xob3at) 2.5 v/2.0 v output buffer (xflob3at) 5 v torelant fail-safe output buffer unit 2.5 v 1.6 1.6 ? ns 2.0 v 2.3 2.3 ? ns ? process 0.25 m, 3/4/5 layered metalization ? i/f levels cmos lvttl compatible ? input modes cmos, lvttl, cmos schmitt, lvttl schmitt, pci-3 v, gated input, fail-safe input 5 v tolerant fail-safe input (xf type only) may be provided with internal pull-up and pull-down resistors (2 resistance values for each) ? output modes normal, 3-state, bi-directional, and fail-safe outputs, pci-3 v, 5 v tolerant fail-safe output (xf type only) ? drive output i ol = 0.1, 1, 3, 6 or 12 ma selectable (hv dd = 3.3 v) i ol = 0.1, 3, 6, or 9 ma selectable (v dd or lv dd = 2.5 v) i ol = 0.05, 0.3, 1, 2, or 3 ma selectable (v dd or lv dd = 2.0 v) ? memory basic cell type ram asynchronous, 1 port; asynchronous, 2 ports synchronous, 1 port; synchronous, 2 ports standard type ram synchronous, 1 port; synchronous, dual ports high density type ram synchronous, 1 port rom synchronous ? built-in level shifter for operation with dual supply voltages internal logic: operates with low voltage input/output buffers: can be interfaced with high and low voltages chapter 1 overview embedded array S1X60000 series epson 3 design guide 1.1.2 internal structure of the S1X60000 series the S1X60000 series is constructed with an msi cell area and an input/output buffer circuit area, as shown in figure 1-1. high density typ e ra m ram rom msi cell area input/output buffer circuit area figure 1-1 outline structure of the S1X60000 series various msi cells and memory blocks can be located in the msi cell area, depending on the desired circuit. these cells can be interconnected in order to implement the desired circuit. the input/output buffer area contains input buffers, output buffers, bi-directional buffers, and power supply cells. in this area, signals are exchanged between external circuits and the units of the S1X60000 series. 1.1.3 structure and types of msis the S1X60000 series is available in basic cell type msi for embedded arrays. memory is also available in various types in addition to the basic cell type ram. these include a highly integrated cell based type ram (with 1 port, dual ports, or high density 1 port) and a rom. the most suitable memory type can be selected in accordance with customer needs. for details on msi cell types, refer to chapter 3, ?msi cells.? for details on memory, refer to chapter 6, ?memory block.? 1.1.4 structure of 5 v tolerant fail-safe cells the 5 v tolerant fail-safe cells of the S1X60000 series allow 5.0 v interfacing without requiring a dedicated power supply. 1.1.5 structure and types of input/output buffers the S1X60000 series has two available types of input/output buffers: standard type input/output buffers (x type) and 5 v tolerant fail-safe input/output buffers (xf type). therefore, customers can choose the type that best suits their system specifications. (note that combined use of the x and xf types is not allowed.) for details about input/output buffers, see chapter 4, ?types of input/output buffers and their use (x type),? and chapter 5, ?types of input/output buffers and their use (xf type).? chapter 1 overview 4 epson embedded array S1X60000 series design guide 1.2 electrical characteristics and specifications 1.2.1 when using standard type input/output buffers (x type) table 1-1 absolute maximum ratings (for a single power supply) (v ss = 0 [v]) parameter symbol limits unit power supply voltage v dd -0.3 to +3.0 v input voltage v i -0.3 to v dd + 0.5 *1 v output voltage v o -0.3 to v dd + 0.5 *1 v output current/pin i out 30 ma storage temperature t stg -65 to +150 c notes *1: possible to use -0.3 v to +4.0 v of n channel open drain bi-directional buffers, input buffers, and fail-safe cells. table 1-2 absolute maximum ratings (for dual power supplies) (v ss = 0 [v]) parameter symbol limits unit hv dd *3 -0.3 to +4.0 v power supply voltage lv dd *3 -0.3 to +3.0 v hv i -0.3 to hv dd + 0.5 *1 v input voltage lv i -0.3 to lv dd + 0.5 *2 v hv o -0.3 to hv dd + 0.5 *1 v output voltage lv o -0.3 to lv dd + 0.5 *2 v output current/pin i out 30 ma storage temperature t stg -65 to +150 c notes *1: possible to use -0.3 v to +4.0 v of n channel open drain bi-directional buffers and input buffers. *2: possible to use -0.3 v to +4.0 v of n channel open drain bi-directional buffers, input buffers, and fail-safe cells. *3: hv dd lv dd chapter 1 overview embedded array S1X60000 series epson 5 design guide table 1-3 recommended operating conditions (for a single power supply at v dd = 2.5 v) (v ss = 0 [v]) parameter symbol min. typ. max. unit power supply voltage v dd 2.30 2.50 2.70 v input voltage v i -0.3 ? v dd + 0.3 *1 v 0 25 70 *2 ambient temperature t a -40 25 85 *3 c normal input rising time *4 t ri ? ? 50 ns normal input falling time *4 t fa ? ? 50 ns schmitt input rising time *4 t ri ? ? 5 ms schmitt input falling time *4 t fa ? ? 5 ms notes *1: possible to use up to 3.9 v of n channel open drain bi-directional buffers, input buffers, and fail-safe cells. *2: the ambient temperature range is recommended for t j = 0 to +85 [ c]. *3: the ambient temperature range is recommended for t j = -40 to +125 [ c]. *4: this is the finite time during which power supply voltage changes from 10% to 90% or vice versa. table 1-4 recommended operating conditions (for a single power supply at v dd = 2.0 v) (v ss = 0 [v]) parameter symbol min. typ. max. unit power supply voltage v dd 1.80 2.00 2.20 v input voltage v i -0.3 ? v dd + 0.3 *1 v 0 25 70 *2 ambient temperature t a -40 25 85 *3 c normal input rising time *4 t ri ? ? 100 ns normal input falling time *4 t fa ? ? 100 ns schmitt input rising time *4 t ri ? ? 10 ms schmitt input falling time *4 t fa ? ? 10 ms notes *1: possible to use up to 3.9 v of n channel open drain bi-directional buffers, input buffers, and fail-safe cells. *2: the ambient temperature range is recommended for t j = 0 to +85 [ c]. *3: the ambient temperature range is recommended for t j = -40 to +125 [ c]. *4: this is the finite time during which power supply voltage changes from 10% to 90% or vice versa. chapter 1 overview 6 epson embedded array S1X60000 series design guide table 1-5 recommended operating conditions (for dual power supplies) (v ss = 0 [v]) parameter symbol min. typ. max. unit power supply voltage (high voltage) hv dd 3.00 3.30 3.60 v power supply voltage (low voltage) lv dd 2.30 2.50 2.70 v hv i -0.3 ? hv dd + 0.3 *1 v input voltage lv i -0.3 ? lv dd + 0.3 *2 v ambient temperature t a 0 -40 25 25 70 *3 85 *4 c normal input rising time *5 t ri ? ? 50 ns normal input falling time *5 t fa ? ? 50 ns schmitt input rising time *5 t ri ? ? 5 ms schmitt input falling time *5 t ra ? ? 5 ms notes *1: possible to use up to 3.9 v of n channel open drain bi-directional buffers and input buffers. *2: possible to use up to 3.9 v of n channel open drain bi-directional buffers, input buffers, and fail-safe cells. *3: the ambient temperature range is recommended for t j = 0 to +85[ c]. *4: the ambient temperature range is recommended for t j = -40 to +125[ c]. *5: this is the finite time during which power supply voltage changes from 10% to 90% or vice versa. table 1-6 recommended operating conditions (for dual power supplies) (v ss = 0 [v]) parameter symbol min. typ. max. unit power supply voltage (high voltage) hv dd 3.00 3.30 3.60 v power supply voltage (low voltage) lv dd 1.80 2.00 2.20 v hv i -0.3 ? hv dd + 0.3 *1 v input voltage lv i -0.3 ? lv dd + 0.3 *2 v ambient temperature t a 0 -40 25 25 70 *3 85 *4 c ht ri ? ? 50 normal input rising time *5 ht ra ? ? 100 ns ht ri ? ? 50 normal input falling time *5 ht ra ? ? 100 ns ht ri ? ? 5 schmitt input rising time *5 ht ra ? ? 10 ms ht ri ? ? 5 schmitt input falling time *5 ht ra ? ? 10 ms notes *1: possible to use up to 3.9 v of n channel open drain bi-directional buffers and input buffers. *2: possible to use up to 3.9 v of n channel open drain bi-directional buffers, input buffers, and fail-safe cells. *3: the ambient temperature range is recommended for t j = 0 to +85[ c]. *4: the ambient temperature range is recommended for t j = -40 to +125[ c]. *5: this is the finite time during which power supply voltage changes from 10% to 90% or vice versa. chapter 1 overview embedded array S1X60000 series epson 7 design guide table 1-7 electrical characteristics (hv dd = 3.3 v 0.3 v, v ss = 0 v, t a = -40 to +85 c) parameter symbol conditions min. typ. max. unit input leaka g e current i li ? -5 ? 5 a off state leakage current i oz ? -5 ? 5 a high level output voltage v oh i oh = -0.1 ma (type s), -1 ma (type m), -3 ma (type 1), -6 ma (type 2), -12 ma (type 3) hv dd = min. hv dd -0.4 ? ? v low level output voltage v ol i ol = 2 ma (type s), 4 ma (type m), 3 ma (type 1), 6 ma (type 2), 12 ma (type 3) hv dd = min. ? ? 0.4 v hi g h level input volta g e v ih1 cmos level, hv dd = max. 2.2 ? ? v low level input voltage v il1 cmos level, hv dd = min. ? 0.8 v hi g h level input volta g e v t1+ cmos schmitt 1.4 ? 2.7 v low level input volta g e v t1- cmos schmitt 0.6 ? 1.8 v h y steresis volta g e v h1 cmos schmitt 0.3 ? ? v hi g h level input volta g e v ih2 lvttl level, hv dd = max 2.0 ? ? v low level input volta g e v il2 lvttl level, hv dd = min ? ? 0.8 v hi g h level input volta g e v t2+ lvttl schmitt 1.1 ? 2.4 v low level input volta g e v t2- lvttl schmitt 0.6 ? 1.8 v h y steresis volta g e v h2 lvttl schmitt 0.1 ? ? v high level input voltage *2 v ih3 pci level, hv dd = max. 1.8 ? ? v low level input voltage *2 v il3 pci level, hv dd = min. ? ? 0.9 v type 1 30 60 (120) *1 144 k ? pull-up resistance p pu v i = 0v type 2 60 120 (240) *1 288 k ? type 1 30 60 (120) *1 144 k ? pull-down resistance p pd v i = hv dd type 2 60 120 (240) *1 288 k ? high level output current *2 i oh3 pci v oh = 0.90 v, hv dd = min. response v oh = 2.52 v, hv dd = max. -36 ? ? ? ? -115 ma low level output current *2 i ol3 pci v ol = 1.80 v, hv dd = min. response v ol = 0.65 v, hv dd = max. 48 ? ? ? ? 137 ma high level maintenance current i bhh bus hold v in = 2.0 v response hv dd = min. ? ? -20 a low level maintenance current i bhl bus hold v in = 0.8 v response hv dd = min. ? ? 17 a high level reversal current i bhho bus hold v in = 0.8 v response hv dd = max. -350 ? ? a low level reversal current i bhlo bus hold v in = 2.0 v response hv dd = max. 210 ? ? a input terminal capacitance c i f = 1 mhz, hv dd = 0 v ? ? 10 pf output terminal capacitance c o f = 1 mhz, hv dd = 0 v ? ? 10 pf input/output terminal capacitance c io f = 1 mhz, hv dd = 0 v ? ? 10 pf notes *1: the value enclosed in ( ) indicates a resistance value when t a = 0 to +70c. *2: compliant with pci standard rev. 2.2 chapter 1 overview 8 epson embedded array S1X60000 series design guide table 1-8 electrical characteristics (v dd or lv dd = 2.5 v 0.2 v, v ss = 0 v, t a = -40 to +85 c) parameter symbol conditions min. typ. max. unit input leakage current i li ? -5 ? 5 a off state leakage current i oz ? -5 ? 5 a high level output voltage v oh i oh = -0.1 ma (type s), -1 ma (type m), -3 ma (type 1), -6 ma (type 2), -9 ma (type 3) v dd = min. v dd -0.4 ? ? v low level output voltage v ol i ol = 0.1 ma (type s), 1 ma (type m), 3 ma (type 1), 6 ma (type 2), 9 ma (type 3) v dd = min. ? ? 0.4 v high level input voltage v ih1 cmos level, v dd = max. 1.7 ? ? v low level input voltage v il1 cmos level, v dd = min. ? ? 0.7 v high level input voltage v t1+ cmos schmitt 0.8 ? 1.9 v low level input voltage v t1- cmos schmitt 0.5 ? 1.3 v hysteresis voltage v h1 cmos schmitt 0.1 ? v type 1 20 50 (100) *1 120 k ? pull-up resistance p pu v i = 0 v type 2 40 100 (200) *1 240 k ? type 1 20 50 (100) *1 120 k ? pull-down resistance p pd v i = hv dd type 2 40 100 (200) *1 240 k ? high level maintenance current i bhh bus hold v in = 1.7 v response v dd = min. ? ? -5 a low level maintenance current i bhl bus hold v in = 0.5 v response v dd = min. ? ? 5 a high level reversal current i bhho bus hold v in = 0.5 v response v dd = max. -280 ? ? a low level reversal current i bhlo bus hold v in = 1.7 v response v dd = max. 170 ? ? a input terminal capacitance c i f = 1 mhz, v dd = 0 v ? ? 10 pf output terminal capacitance c o f = 1 mhz, v dd = 0 v ? ? 10 pf input/output terminal capacitance c io f = 1 mhz, v dd = 0 v ? ? 10 pf note *1: the value enclosed in ( ) indicates a resistance value when t a = 0 to +70c. chapter 1 overview embedded array S1X60000 series epson 9 design guide table 1-9 electrical characteristics (v dd or lv dd = 2.0 v 0.2 v, v ss = 0 v, t a = -40 to +85 c) parameter symbol conditions min. typ. max. unit input leakage current i li ? -5 ? 5 a off state leakage current i oz ? -5 ? 5 a high level output voltage v oh i oh = -0.05 ma (type s), -0.3 ma (type m), -1 ma (type 1), -2 ma (type 2), -3 ma (type 3) v dd = min. v dd -0.2 ? ? v low level output voltage v ol i ol = 0.05 ma (type s), 0.3 ma (type m), 1 ma (type 1), 2 ma (type 2), 4 ma (type 3) v dd = min. ? ? 0.2 v high level input voltage v ih1 cmos level, v dd = max. 1.6 ? ? v low level input voltage v il1 cmos level, v dd = min. ? ? 0.3 v high level input voltage v t1+ cmos schmitt 0.4 ? 1.6 v low level input voltage v t1- cmos schmitt 0.3 ? 1.4 v hysteresis voltage v h1 cmos schmitt 0 ? ? v type 1 30 70 200 k ? pull-up resistance p pu v i = 0 v type 2 60 140 400 k ? type 1 30 70 200 k ? pull-down resistance p pd v i = v dd type 2 60 140 400 k ? high level maintenance current i bhh bus hold v in = 1.6 v response v dd = min. ? ? -2 a low level maintenance current i bhl bus hold v in = 0.3 v response v dd = min. ? ? 2 a high level reversal current i bhho bus hold v in = 0.3 v response v dd = max. -100 ? ? a low level reversal current i bhlo bus hold v in = 1.6 v response v dd = max. 100 ? ? a input terminal capacitance c i f = 1 mhz, v dd = 0 v ? ? 10 pf output terminal capacitance c o f = 1 mhz, v dd = 0 v ? ? 10 pf input/output terminal capacitance c io f = 1 mhz, v dd = 0 v ? ? 10 pf chapter 1 overview 10 epson embedded array S1X60000 series design guide 1.2.2 when using 5 v tolerant fail-safe input/output buffers (xf type) table 1-10 absolute maximum ratings (for dual power supplies) (v ss = 0 [v]) parameter symbol limits unit hv dd *3 -0.3 to +4.0 v power supply voltage lv dd *3 -0.3 to +2.5 v hv i -0.3 to hv dd + 0.5 *1 v input voltage lv i -0.3 to lv dd + 0.5 *2 v hv o -0.3 to hv dd + 0.5 *1 v output voltage lv o -0.3 to lv dd + 0.5 *2 v output current/pin i out 30 ma storage temperature t stg -65 to +150 c notes *1: possible to use -0.3 v to +4.0 v of n channel open drain bi-directional buffers and input buffers, and -0.3 v to 5.5 v of 5 v tolerant fail-safe cells. *2: possible to use -0.3 v to +4.0 v of n channel open drain bi-directional buffers, input buffers, and fail-safe cells. *3: hv dd lv dd chapter 1 overview embedded array S1X60000 series epson 11 design guide table 1-11 recommended operating conditions (for dual power supplies) (v ss = 0 [v]) parameter symbol min. typ. max. unit power supply voltage (high voltage) hv dd 3.00 3.30 3.60 v power supply voltage (low voltage) lv dd 2.30 2.50 2.70 v hv i -0.3 ? hv dd + 0.3 *1 v input voltage lv i -0.3 ? lv dd + 0.3 *2 v 0 25 70 *3 c ambient temperature t a -40 25 85 *4 normal input rising time *5 t ri ? ? 50 ns normal input falling time *5 t fa ? ? 50 ns schmitt input rising time *5 t ri ? ? 5 ms schmitt input falling time *5 t ra ? ? 5 ms notes *1: possible to use up to 3.9 v of n channel open drain bi-directional buffers and input buffers and up to 5.5 v of 5 v tolerant fail-safe cells. *2: possible to use up to 3.9 v of n channel open drain bi-directional buffers, input buffers, and fail-safe cells. *3: the ambient temperature range is recommended for t j = 0 to +85[ c]. *4: the ambient temperature range is recommended for t j = -40 to +125[ c]. *5: this is the finite time during which power supply voltage changes from 10% to 90% or vice versa. table 1-12 recommended operating conditions (for dual power supplies) (v ss = 0 [v]) parameter symbol min. typ. max. unit power supply voltage (high voltage) hv dd 3.00 3.30 3.60 v power supply voltage (low voltage) lv dd 1.80 2.00 2.20 v hv i -0.3 ? hv dd + 0.3 *1 v input voltage lv i -0.3 ? lv dd + 0.3 *2 v 0 25 70 *3 c ambient temperature t a -40 25 85 *4 c normal input rising time *5 t ri ? ? 50 ns normal input falling time *5 t ra ? ? 50 ns schmitt input rising time *5 t ri ? ? 5 ms schmitt input falling time *5 t ra ? ? 5 ms notes *1: possible to use up to 3.9 v of n channel open drain bi-directional buffers and input buffers and up to 5.5 v of 5 v tolerant fail-safe cells. *2: possible to use up to 3.9 v of n channel open drain bi-directional buffers, input buffers, and fail-safe cells. *3: the ambient temperature range is recommended for t j = 0 to +85[ c]. *4: the ambient temperature range is recommended for t j = -40 to +125[ c]. *5: this is the finite time during which power supply voltage changes from 10% to 90% or vice versa. chapter 1 overview 12 epson embedded array S1X60000 series design guide table 1-13 electrical characteristics (1/2) (hv dd = 3.3 v 0.3 v, v ss = 0 v, t a = -40 to +85 c) parameter symbol conditions min. typ. max. unit input leakage current i li ? -5 ? 5 a off state leakage current i oz ? -5 ? 5 a input leakage current (5 v tolerant fail-safe cell) i lif v in = 5.5 v -10 ? 10 a off state leakage current (5 v tolerant fail-safe cell) i ozf v in = 5.5 v -10 ? 10 a high level output voltage (ordinary cell) v oh1 i oh = -0.1 ma (type s), -1 ma (type m), -3 ma (type 1), -6 ma (type 2), -12 ma (type 3) hv dd = min. hv dd -0.4 ? ? v high level output voltage (5 v tolerant fail-safe cell) v oh2 i oh = -3 ma (type 1), -6 ma (type 2), -12 ma (type 3) hv dd = min. hv dd -1.0 ? ? v low level output voltage v ol1 i ol = -0.1 ma (type s), -1 ma (type m), -3 ma (type 1), -6 ma (type 2), -12 ma (type 3) hv dd = min. ? ? 0.4 v high level input voltage v ih1 cmos level, hv dd = max. 2.2 ? ? v low level input voltage v il1 cmos level, hv dd = min. ? 0.8 v high level input voltage v t1+ cmos schmitt 1.4 ? 2.7 v low level input voltage v t1- cmos schmitt 0.6 ? 1.8 v hysteresis voltage v h1 cmos schmitt 0.3 ? ? v high level input voltage v ih2 lvttl level, hv dd = max. 2.0 ? ? v low level input voltage v il2 lvttl level, hv dd = min. ? ? 0.8 v high level input voltage v t2+ lvttl schmitt 1.1 ? 2.4 v low level input voltage v t2- lvttl schmitt 0.6 ? 1.8 v hysteresis voltage v h2 lvttl schmitt 0.1 ? ? v high level input voltage *2 v ih3 pci level, hv dd = max. 1.8 ? ? v low level input voltage *2 v il3 pci level, hv dd = min. ? ? 0.9 v type 1 30 60 (120) *1 144 k ? pull-up resistance p pu v i = 0 v type 2 60 120 (240) *1 288 k ? type 1 30 60 (120) *1 144 k ? pull-down resistance p pd v i = hv dd type 2 60 120 (240) *1 288 k ? note *1: the value enclosed in ( ) indicates a resistance value when t a = 0 to +70c. *2: compliant with pci standard rev. 2.2 chapter 1 overview embedded array S1X60000 series epson 13 design guide table 1-13 electrical characteristics (2/2) (hv dd = 3.3 v 0.3 v, v ss = 0 v, t a = -40 to +85 c) parameter symbol conditions min. typ. max. unit high level output voltage *2 i oh3 pci v n = 0.90 v, hv dd = min. response v oh = 2.52 v, hv dd = max. -36 ? ? ? ? -115 ma ma low level output voltage *2 i ol3 pci v ol = 1.80 v, hv dd = min. response v ol = 0.65 v, hv dd = max. 48 ? ? ? ? -137 ma ma high level maintenance current i bhh bus hold v in = 2.0 v response hv dd = min. ? ? -20 a low level maintenance current i bhl bus hold v in = 0.8 v response hv dd = min. ? ? 17 a high level reversal current i bhho bus hold v in = 0.8 v response hv dd = max. -350 ? ? a low level reversal current i bhlo bus hold v in = 2.0 v response hv dd = max. 210 ? ? a input terminal capacitance c i f = 1 mhz, hv dd = 0 v ? ? 12 pf output terminal capacitance c o f = 1 mhz, hv dd = 0 v ? ? 12 pf input/output terminal capacitance c io f = 1 mhz, hv dd = 0 v ? ? 12 pf note *2: compliant with pci standard rev. 2.2 chapter 1 overview 14 epson embedded array S1X60000 series design guide table 1-14 electrical characteristics (lv dd = 2.5 v 0.2 v, v ss = 0 v, t a = -40 to +85 c) parameter symbol conditions min. typ. max. unit input leakage current i li ? -5 ? 5 a off state leakage current i oz ? -5 ? 5 a high level output voltage v oh1 i oh = -0.1 ma (type s), -1 ma (type m), -3 ma (type 1), -6 ma (type 2), -9 ma (type 3) lv dd = min. lv dd -0.4 ? ? v low level output voltage v ol1 i ol = 0.1 ma (type s), 1 ma (type m), 3 ma (type 1), 6 ma (type 2), 9 ma (type 3) v dd = min. ? ? 0.4 v high level input voltage v ih1 cmos level, v dd = max. 1.7 ? ? v low level input voltage v il1 cmos level, v dd = min. ? ? 0.7 v high level input voltage v t1+ cmos schmitt 0.8 ? 1.9 v low level input voltage v t1- cmos schmitt 0.5 ? 1.3 v hysteresis voltage v h1 cmos schmitt 0.1 ? ? v type 1 20 50 (100) *1 120 k ? pull-up resistance p pu v i = 0 v type 2 40 100 (200) *1 240 k ? type 1 20 50 (100) *1 120 k ? pull-down resistance p pd v i = lv dd type 2 40 100 (200) *1 240 k ? high level maintenance current i bhh bus hold v in = 1.7 v response v dd = min. ? ? -5 a low level maintenance current i bhl bus hold v in = 0.7 v response v dd = min. ? ? 5 a high level reversal current i bhho bus hold v in = 0.5 v response v dd = max. -280 ? ? a low level reversal current i bhlo bus hold v in = 1.7 v response v dd = max. 170 ? ? a input terminal capacitance c i f = 1 mhz, lv dd = 0 v ? ? 12 pf output terminal capacitance c o f = 1 mhz, lv dd = 0 v ? ? 12 pf input/output terminal capacitance c io f = 1 mhz, lv dd = 0 v ? ? 12 pf note *1: the value enclosed in ( ) indicates a resistance value when t a = 0 to +70c. chapter 1 overview embedded array S1X60000 series epson 15 design guide table 1-15 electrical characteristics (lv dd = 2.0 v 0.2 v, v ss = 0 v, t a = -40 to +85 c) parameter symbol conditions min. typ. max. unit input leakage current i li ? -5 ? 5 a off state leakage current i oz ? -5 ? 5 a high level output voltage v oh1 i oh = -0.05 ma (type s), -0.3 ma (type m), -1 ma (type 1), -2 ma (type 2), -3 ma (type 3) lv dd = min. lv dd -0.2 ? ? v low level output voltage v ol1 i ol = 0.05 ma (type s), 0.3 ma (type m), 1 ma (type 1), 2 ma (type 2), 3 ma (type 3) lv dd = min. ? ? 0.2 v high level input voltage v ih1 cmos level, v dd = max. 1.6 ? ? v low level input voltage v il1 cmos level, v dd = min. ? ? 0.3 v high level input voltage v t1+ cmos schmitt 0.4 ? 1.6 v low level input voltage v t1- cmos schmitt 0.3 ? 1.4 v hysteresis voltage v h1 cmos schmitt 0 ? ? v type 1 30 70 200 k ? pull-up resistance p pu v i = 0 v type 2 60 140 400 k ? type 1 30 70 200 k ? pull-down resistance p pd v i = lv dd type 2 60 140 400 k ? high level maintenance current i bhh bus hold v in = 1.6 v response lv dd = min. ? ? -2 a low level maintenance current i bhl bus hold v in = 0.3 v response lv dd = min. ? ? 2 a high level reversal current i bhho bus hold v in = 0.3 v response lv dd = max. -100 ? ? a low level reversal current i bhlo bus hold v in = 1.6 v response lv dd = max. 100 ? ? a input terminal capacitance c i f = 1 mhz, lv dd = 0 v ? ? 12 pf output terminal capacitance c o f = 1 mhz, lv dd = 0 v ? ? 12 pf input/output terminal capacitance c io f = 1 mhz, lv dd = 0 v ? ? 12 pf chapter 1 overview 16 epson embedded array S1X60000 series design guide 1.3 estimating the quiescent current the quiescent current for cells in the S1X60000 series can be roughly estimated using the equation shown below. when calculating the quiescent current, please assume ambient temperature (t a ) = chip temperature (t j ). the quiescent current depends on the off current of each transistor. because the quiescent current for the entire chip cannot easily be calculated simultaneously, divide the chip into several blocks in the calculation of the quiescent current, and use the sum total of all blocks as the chip?s quiescent current. i dds (t j = 85 c ) = i qb c + i qbm + i qio 1.3.1 quiescent current in the random logic part (i qbc ) table 1-16 lists the quiescent current per 1k gate in the S1X60000 series. table 1-16 quiescent current per 1k gate (t j = 85 c) v dd = 2.70 v v dd = 2.20 v unit i qbc 7.94 10 -7 6.35 10 -7 a 1.3.2 quiescent current of basic cell type ram (i qbm ) the quiescent current values of the primary basic cell type rams in the S1X60000 series are listed in table 1-17. (to find quiescent current when v dd = 2.20 v and t j = 85c, multiply the values shown below by 0.8.) (for the quiescent current values of rams not listed here, use the quiescent current value of the ram that is closest in structure to those rams. if more detailed information on quiescent current values is required, please contact the sales division of epson.) table 1-17 quiescent current values of basic cell type ram (common to 1 port ram and 2 port ram, v dd = 2.70 v, t j = 85 c) ? asynchronous ram 64 word 128 word 256 word 512 word unit 8 bit 2.19 10 -6 3.73 10 -6 6.82 10 -6 12.99 10 -6 a 16 bit 3.08 10 -6 5.24 10 -6 9.54 10 -6 18.16 10 -6 a 32 bit 4.87 10 -6 8.25 10 -6 14.99 10 -6 28.48 10 -6 a 64 bit 8.46 10 -6 14.27 10 -6 25.89 10 -6 49.14 10 -6 a ? synchronous ram 64 word 128 word 192 word 256 word unit 8 bit 2.19 10 -6 3.73 10 -6 5.27 10 -6 6.82 10 -6 a 16 bit 3.08 10 -6 5.24 10 -6 7.39 10 -6 9.54 10 -6 a 24 bit 3.98 10 -6 6.74 10 -6 9.51 10 -6 12.27 10 -6 a 32 bit 4.87 10 -6 8.25 10 -6 11.62 10 -6 14.99 10 -6 a chapter 1 overview embedded array S1X60000 series epson 17 design guide 1.3.3 quiescent current of input/output buffers (i qio ) the quiescent current values flowing in input/output buffers can be roughly estimated by using the values listed in table 1-18 for the calculation formula shown on the next page. (make sure the input signals for the input and bi-directional buffers are fixed to v ss or v dd (lv dd or hv dd ). if buffers with pull-up and pull-down resistors have been selected, leave the pins open.) for systems with dual power supplies, calculate the quiescent current for the h- and l-voltage buffers separately. note: when connecting v dd (lv dd or hv dd ) to the nc pin, be sure to add the number of nc pins (as power supply cells) to the number of input/output cells. table 1-18 quiescent current value per input/output buffer (t j = 85 c) quiescent current value unit v dd = 3.60v 200 10 -9 a v dd = 2.70v 50 10 -9 a v dd = 2.20v 45 10 -9 a quiescent current value of input / output buffer = (values in table 1-18) (number of output cells + number of bi-directional cells + number of v dd (hv dd or lv dd ) power supply cells) chapter 1 overview 18 epson embedded array S1X60000 series design guide calculation example: find the quiescent current value for the following case. ? power supply voltage: hv dd / lv dd = 3.3 v / 2.5 v ? i/o cells v ss : 12 hv dd : 12 lv dd : 12 h-voltage input cells: 30 h-voltage output cells: 40 h-voltage bi-directional cells: 60 l-voltage input cells: 30 l-voltage output cells: 20 l-voltage bi-directional cells: 40 ? basic cell type 2 port ram: 256 words 16 bits, 4 pcs. (synchronous ram) 128 words 8 bits, 6 pcs. (synchronous ram) ? cell based logic: 1240k gates because this is a dual power supply system, first find the quiescent current for the lv dd system. from table 1-16, the quiescent current value of the cell-based logic is i qbc = 7.94 10 -7 1240 = 984.56 10 -6 [a] (v dd = 2.7 v, t j = 85 c) next, find the quiescent current value of the basic cell type rams. from table 1-17, the quiescent current value per piece of ram is 256 word 16 bit ... 9.54 10 -6 [a] 128 word 8 bit ... 3.73 10 -6 [a] therefore, the quiescent current value of the basic cell type rams is i qbm = (9.54 10 -6 4) + (3.73 10 -6 6) = 38.16 10 -6 + 22.38 10 -6 = 60.54 10 -6 [a] (v dd = 2.7 v, t j = 85 c) next, find the quiescent current value of the input/output buffers using the equation for quiescent current values shown above. i qio = 50 10 -9 (20 + 40 + 12) = 3.60 10 -6 [a] from the quiescent current values obtained thus far, find the quiescent current value of the lv dd system. i q (lv dd ) = i qbc + i qbm + i qio = 984.56 10 -6 + 60.54 10 -6 + 3.6 10 -6 = 1048.7 10 -6 [a] next, find the quiescent current value of the hv dd system. to find the quiescent current value of the hv dd system, simply calculate the quiescent current flowing in the input/output buffers. i q (hv dd ) = 200 10 -9 (40 + 60 + 12) = 22.40 10 -6 [a] chapter 1 overview embedded array S1X60000 series epson 19 design guide from the above calculation results, the quiescent current values to be obtained in this example are i q (lv dd ) = 1048.7 10 -6 [a] i q (hv dd ) = 22.40 10 -6 [a] 1.3.4 temperature characteristics of quiescent current the quiescent current values at temperatures other than t j = 85[ c] can be approximately calculated using the equation shown below. (however, this only applies when t j = -40 to 85 [c]. when t j = 125c, use a temperature coefficient of 7 to calculate the equation below. when t j = 85 to 125 [c], please contact the nearest epson office or distributor. i dds (t j ) = i dds (t j = 85 c) x temperature coefficient = i dds (t j = 85 c) x 10 (however, t j = 0 to 125c) calculation example: for a chip whose quiescent current is 630 [a] when v dd = 2.5 v 0.2 v and t j = 85 [c], calculate the approximate value of quiescent current when t j = 50 [c] as follows: i dds (t j = 50 c) = i dds (t j = 85 c) 10 = 630 0.261 = 164.43 [ a] for dual-power supply systems, the sum of quiescent currents for the voltages used constitutes the total amount of quiescent current. (hi dds + li dds ) t j - 85 60 50 - 85 60 chapter 1 overview 20 epson embedded array S1X60000 series design guide 1.4 embedded array development flow the embedded arrays are developed jointly by customers and epson. customers perform work based on the cell libraries and various design materials supplied by epson. this work includes system design, circuit design, and pattern design. before these designs can be interfaced to epson, customers are requested to check them based on the data release checklist included herein. after completion of that check, the necessary data and documentation may be presented to epson. customers conduct simulations of said designs using eda software or epits * available on hand, and epson undertakes subsequent work following placement and routing. note *: epits is epson?s asic library that runs on ms-windows nt4.0 and sun-solaris platforms. epits currently supports the following types of eda software: ? verilog-xl (*1) ? design compiler (*2) note *1: verilog-xl is a registered trademark of cadence design systems corporation, usa. *2: design compiler is a registered trademark of synopsys, inc., usa. for more information, please contact the sales division of epson. chapter 1 overview embedded array S1X60000 series epson 21 design guide the process flow of the embedded array development process is shown below. customer distributor (interface) epson product plan functional spec. circuit design test pattern design logic check (simulation) timing check (simulation) automatic place & rout (post simulation) make masks ts (test sample) fabrication es (engineering sample) fabrication mp setup mp delivery spec. publication standard-cell development request simulation file simulation list customer spec. sign off es (ts) prototype-evaluation approval notification delivery spec. delivery spec. approval notification schematic pin assignment timing wave form marking-diagram p/o verification* ng ng delay time analysis delay time analysis ok ng ok functional evaluation ng overall evaluation ng ok ok delivery spec. approval operations enclosed in ( ) are performed only when so requested by customers. verification verification es (ts) approval notification chapter 2 estimating the gate density 22 epson embedded array S1X60000 series design guide chapter 2 estimating the gate density this chapter describes the procedure for estimating the circuit size after cutting out circuits from the customer?s system, and then estimating an approximate bulk size. the precautions to be taken when performing this work are also described. 2.1 dividing up logic between chips when cutting out circuits from the customer?s system, care must be taken with respect to the following points. ? precautions to be taken (1) logic size to be integrated (gate count) (2) number of i/o pins required (pin count) (3) package to be used (4) power consumption generally speaking, as the circuit size increases, so does the power consumption of the circuit and the number of input/output pins on it. if the circuit size is significantly large, the circuit may be divided into multiple chips rather than being integrated into a single chip. this helps reduce the total cost and the power consumption of the circuit. 2.2 estimating the gate counts used the circuit size is estimated by counting the total number of basic cells for each cell (bc counts). the ?embedded array S1X60000 series msi cell library? lists the bc counts of each cell. refer to this manual to obtain the sum total of bc counts for a circuit. 2.3 estimating the number of input/output pins after the number of gates used in cells has been estimated, calculate the number of actually used input/output pins. when performing this calculation, make sure the test pins and power supply pins on basic cell type ram and cell based-type ram and rom are included in the pin counts. to estimate the number of power supply pins, use the method described in section 9.11, ?pin layout and simultaneous operation.? chapter 2 estimating the gate density embedded array S1X60000 series epson 23 design guide 2.4 bulk list the optimum master (bulk) is determined from the gate counts used, ram, functional cells, number of input/output pins (including power supply pins), and package to be used. table 2-1 lists the primary bulks in the S1X60000 series. table 2-1 list of representative bulks basic cell arrays cell usage efficiency bulk bc counts pad counts x direction y direction 3 layers 4 layers 5 layers a 99,220 112 605 164 60 70 80 b 171,720 148 795 216 60 70 80 c 284,394 188 1,023 278 50 65 75 d 400,290 224 1,213 330 50 65 75 e 595,362 272 1,481 402 50 65 75 f 831,572 284 1,747 476 40 50 60 g 1,234,820 344 2,129 580 40 50 60 h 1,587,754 388 2,413 658 40 50 60 i 1,902,960 424 2,643 720 40 50 60 j 2,519,604 488 3,043 828 40 50 60 chapter 3 msi cells 24 epson embedded array S1X60000 series design guide chapter 3 msi cells 3.1 msi cell types below is a list of the functions of the msi cell types in the S1X60000 series. for more information, please contact the sales division of epson. list of cell functions in the S1X60000 series ? buffer ? inverter ? delay line ? and gate input (2/3/4) /input (2/3/4) with inverted input (1/2/3) input (5/6/8) ? nand gate input (2/3/4) /input (2/3/4) with inverted input (1/2/3) input (5/6/8) ? or gate input (2/3/4) /input (2/3/4) with inverted input (1/2/3) input (5/6/8) ? nor gate input (2/3/4) /input (2/3/4) with inverted input (1/2/3) input (5/6/8) ? exclusive or/nor input (2/3) ? and-nor gates 2-and-nor input (3/4/6/8) 3-and-nor input (4/6) ? and-or gates 2-and-or input (3/4/5/6/8) 3-and-or input (4/5/6) 4-and-or input (8) ? or-and gates 2-or-and input (3/4/5/6/8) 3-or-and input (4/5/6) 4-or-and input (8) ? or-nand gates 2-and-or input (3/4/8) 3-and-or input (4/6) chapter 3 msi cells embedded array S1X60000 series epson 25 design guide ? multi-function gates 2-or 2-and 4-input or gate 2-and 2-or 4-input and gate 2-or 2-nand 4-input or gate 2-and 2-nor 4-input and gate ? majority gates 2 of 3/inverted 2 of 3 ? test function special delay cell for ac testing test mode control circuit ? clock tree root buffer buffer/inverter ? gated clock 2-input and gate 2-input or gate 2-input nand gate 2-input nor gate inverter selector/multiplexer ? flip flops d-flip flop set/reset synchronous enabled output q negative clock scan quadruple (reset/reset and q output only) octal (reset/reset and q output only) jk-flip flop set/reset output q scan rs-flip flop nand-type/nor-type ? latches preset/reset output m negative clock quadruple (reset/reset and m output only) octal with enable ? adder 1-bit full adder/power (2/4) 4-bit full adder 4-bit full adder with fast carry chapter 3 msi cells 26 epson embedded array S1X60000 series design guide ? comparators 4-bit magnitude comparator with enable 8-bit magnitude comparator with enable ? counters 4bit binary up counter with reset, load and enable 4bit binary up counter with reset and enable 4bit binary up/down counter with load and enable 4bit binary up/down counter with reset, load and enable ? decoders 3-line to 8-line 2-line to 4-line enable ? selectors/multiplexers 2-line to 1-line 4-line to 1-line enable quadruple 2-line to 1-line enable negative output ? shift registers 8-bit si/po shift register with reset 8-bit si/po pi/so shift register with reset, load and enable 4-bit si/po pi/so shift register with reset, load and enable 4-bit bi-directional universal shift register with reset ? bus cells latch (quadruple/octal) 1bit ram 3-state buffer -low enable/high enable bus driver chapter 4 types of input/output buffers and their use (x type) embedded array S1X60000 series epson 27 design guide chapter 4 types of input/output buffers and their use (x type) this chapter describes in detail how the input buffers, output buffers, and bi-directional buffers of the six60000 series (x type) are constructed. 4.1 types of input/output buffers the S1X60000 series (x type) offers a wide selection of cells to choose from depending on the input interface level, whether schmitt trigger input is needed and pull-up/pull-down resistors are included, output drive capability, and whether noise reduction measures are incorporated. choose the input/output buffers that best suit your system by considering the items described below. note that there are two methods of using input/output buffers: when operating buffers with a single power supply (2.5 v or 2.0 v), or operating buffers with dual power supplies (3.3 v/2.5 v, or 3.3 v/2.0 v). 4.1.1 selecting input/output buffers (1) selecting an input buffer a) whether the necessary interface level is cmos level or lvttl level b) whether schmitt trigger input is needed (i.e., whether hysteresis characteristics are required) c) whether internal pull-up/pull-down resistors are needed (2) selecting an output buffer a) necessary amounts of output drive currents (i ol /i oh ) b) whether noise reduction measures are needed c) whether a bus hold circuit is needed (3) selecting a bi-directional buffer consider items (1) and (2) above to select a bi-directional buffer. ? input interface level (1) when hv dd = 3.3 v input level lvttl level, cmos level, lvttl schmitt, cmos schmitt, pci-3v* output level cmos level, pci-3v* (2) when v dd or lv dd = 2.5 v input level cmos level, cmos schmitt output level cmos level chapter 4 types of input/output buffers and their use (x type) 28 epson embedded array S1X60000 series design guide (3) when v dd or lv dd = 2.0 v input level cmos level, cmos schmitt output level cmos level note: lvttl level input cannot be used for single-power supply systems. * for the pci interface, please contact the sales division of epson. ? output drive capability see tables 1-7, 1-8, and 1-9 for electrical characteristics. ? pull-up/pull-down resistors see tables 1-7, 1-8, and 1-9 for electrical characteristics. 4.1.2 bus hold circuit to ensure that the output pins and bi-directional pins will not enter a high-impedance state, S1X60000 (x type) series has available an input/output buffer that comes equipped with a bus hold facility to hold the data at the output pins. however, because the bus hold circuit?s retention capability is suppressed so as not to adversely affect the ordinary operation of the cell, do not use the output data held by the circuit as valid data. the retained data may easily change state when any data is supplied from an external circuit. for the bus hold circuit?s output retention current, refer to table 1-7 through 1-9. chapter 4 types of input/output buffers and their use (x type) embedded array S1X60000 series epson 29 design guide 4.2 input/output buffers for a single power supply when the input/output buffers are used with a single power supply, the useful power supply voltage is 2.5 v or 2.0 v only. 4.2.1 input buffers table 4-1 rated pull-up/pull-down resistance values at each voltage resistance value type of pull-up/pull-down resistor v dd = 2.5 v v dd = 2.0 v unit type 1 50 70 k ? type 2 100 140 k ? table 4-2 input buffers list cell name *1 input level whether pull-up/pull-down resistors are included xibc xibcp# xibcd# cmos cmos cmos none pull-up resistor included pull-down resistor included xibh xibhp# xibhd# cmos schmitt cmos schmitt cmos schmitt none pull-up resistor included pull-down resistor included notes *1: the # denotes 1 or 2, with the pull-up/pull-down resistance values corresponding to type 1 and type 2, respectively (for details, refer to table 4-1). chapter 4 types of input/output buffers and their use (x type) 30 epson embedded array S1X60000 series design guide 4.2.2 output buffers tables 4-4 and 4-6 list the output buffers. table 4-3 rated i oh and i ol values at each voltage i oh *1 /i ol *2 type of output current v dd = 2.5 v v dd = 2.0 v unit type s -0.1/0.1 -0.05/0.05 ma type m -1/1 -0.3/0.3 ma type 1 -3/3 -1/1 ma type 2 -6/6 -2/2 ma type 3 -9/9 -3/3 ma notes *1: v oh = v dd - 0.4 v (v dd = 2.5 v) or v dd - 0.2 v (v dd = 2.0 v) *2: v ol = 0.4 v (v dd = 2.5 v) or 0.2 v (v dd = 2.0 v) table 4-4 output buffers list function i oh /i ol cell name *1, *2 normal output type s type m type 1 type 2 type 3 xob#t normal output for high speed type 3 xob3at normal output for low noise type 3 xob3bt 3-state output type s type m type 1 type 2 type 3 xtb#t 3-state output for high speed type 3 xtb3at 3-state output for low noise type 3 xtb3bt 3-state output (bus hold circuit) type m type 1 type 2 type 3 xtb$ht 3-state output for high speed (bus hold circuit) type 3 xtb3aht 3-state output for low noise (bus hold circuit) type 3 xtb3bht notes *1: note that # denotes s, m, 1, 2, or 3; $ denotes m, 1, 2, or 3 with their i oh /i ol values corresponding to type s, type m, type 1, type 2, and type 3, respectively (for details, refer to table 4-3). *2: in addition to the configurations shown in table 4-4, the output buffers may be configured without test pins. customers desiring to use such configurations should direct inquiries to epson. chapter 4 types of input/output buffers and their use (x type) embedded array S1X60000 series epson 31 design guide table 4-5 rated i ol values at each voltage i ol *1 type of output current v dd = 2.5 v v dd = 2.0 v unit type 1 3 1 ma type 2 6 2 ma type 3 9 3 ma note *1: v ol = 0.4 v (v dd = 2.5 v) or v dd - 0.2 v (v dd = 2.0 v) table 4-6 n channel open drain output buffers list function i ol cell name *1, *2 normal output type 1 type 2 type 3 xod#t notes *1: the # denotes 1, 2, or 3 with the i ol values corresponding to type 1, type 2, and type 3, respectively (for details, refer to table 4-5). *2: in addition to the configurations in table 4-6, the n channel open drain output buffers may be configured without test pins. customers desiring to use such configurations should direct inquiries to epson. chapter 4 types of input/output buffers and their use (x type) 32 epson embedded array S1X60000 series design guide 4.2.3 bi-directional buffers tables 4-7 and 4-8 list bi-directional buffers. table 4-7 bi-directional buffers list input level function i oh /i ol cell name *1, *2 bi-directional output type s type m type 1 type 2 type 3 xbc#t bi-directional output for high speed type 3 xbc3at cmos bi-directional output for low noise type 3 xbc3bt bi-directional output type s type m type 1 type 2 type 3 xbh#t bi-directional output for high speed type 3 xbh3at cmos schmitt bi-directional output for low noise type 3 xbh3bt bi-directional output (bus hold circuit) type m type 1 type 2 type 3 xbc$ht bi-directional output for high speed (bus hold circuit) type 3 xbc3aht cmos bi-directional output for low noise (bus hold circuit) type 3 xbc3bht bi-directional output (bus hold circuit) type m type 1 type 2 type 3 xbh$ht bi-directional output for high speed (bus hold circuit) type 3 xbh3aht cmos schmitt bi-directional output for low noise (bus hold circuit) type 3 xbh3bht notes *1: note that # denotes s, m, 1, 2, or 3; $ denotes m, 1, 2, or 3 with their i oh /i ol values corresponding to type s, type m, type 1, type 2, and type 3, respectively (for details, refer to table 4-3). *2: in addition to the configurations shown in table 4-7, the bi-directional buffers may be configured with pull-up/pull-down resistors or without test pins. customers desiring to use such configurations should direct inquiries to epson. chapter 4 types of input/output buffers and their use (x type) embedded array S1X60000 series epson 33 design guide table 4-8 n channel open drain bi-directional buffers list input level function i ol cell name *1, *2 cmos bi-directional output type 1 type 2 type 3 xbdc#t cmos schmitt bi-directional output type 1 type 2 type 3 xbdh#t notes *1: the # denotes 1, 2, or 3 with the i ol values corresponding to type 1, type 2, and type 3, respectively (for details, refer to table 4-5). *2: in addition to the configurations shown in table 4-8, the n channel open drain bi-directional buffers may be configured without test pins. customers desiring to use such configurations should direct inquiries to epson. chapter 4 types of input/output buffers and their use (x type) 34 epson embedded array S1X60000 series design guide 4.2.4 fail-safe cells 4.2.4.1 overview the S1X60000 series (x type) fail-safe cells allow signals above the power supply voltage to be interfaced, even while power is supplied. furthermore, no leakage current flows in those cells, despite the fact that the signals are interfaced while the power is cut off. therefore, they provide greater freedom of design than ever before. (in dual-power supply systems, these are used as lv dd system cells.) 4.2.4.2 features (1) the fail-safe cells can be positioned as desired by customers. (2) even when input signals above the power supply voltage are applied while power is supplied, no input leakage current flows. (for input buffers or bi-directional buffers with pull-up resistors, however, a small input leakage current of approximately 30 a may flow due to their circuit configuration.) (3) even when input signals are applied from the outside while the power is cut off, no input leakage current flows. (4) fail-safe cells with two different input levels, the cmos level and the cmos schmitt level, are available. (5) because the fail-safe cells are completely cmos structured, the power consumption can be suppressed to a minimum. 4.2.4.3 usage precautions (1) about input i/o cells ? for input buffers without resistors or with pull-down resistors, ordinary input buffers may be used directly as fail-safe cells. ? if input buffers with pull-up resistors are needed, always be sure to use fail-safe cells (however, a small input leakage current of approximately 30 a may flow due to their circuit configuration). (2) about output i/o cells ? provided that the output buffers are placed in high-z state or the bi-directional buffers are placed in input mode, no input leakage current may flow even when input signals above the power supply voltage are applied while power is supplied. ? if signals above the power supply voltage are applied while the bi-directional buffers are placed in output mode, an input leakage current flows as in ordinary input/output buffers. the same applies when pull-up resistors above the power supply voltage exist outside the chip. (if a high logic level above the power supply voltage is needed, use open drain type input/output buffers, with pull-up resistors added external to the chip in order to pull-up the logic level high.) chapter 4 types of input/output buffers and their use (x type) embedded array S1X60000 series epson 35 design guide (3) although the fail-safe cells can receive high voltage signals above the lsi?s operating voltage, be aware that the signal voltages applied to the fail-safe cells must never exceed their rated maximum voltage. 4.2.4.4 list of cells table 4-9 fail-safe input buffers list cell name *1, *2 input level whether pull-up resistors are included xibbp# cmos pull-up resistor included xibgp# cmos schmitt pull-up resistor included notes *1: the # denotes 1 or 2, with the pull-up resistance values corresponding to type 1 and type 2, respectively (for details, refer to table 4-1). table 4-10 fail-safe output buffers list function i oh /i ol cell name *1, *2 3-state output type 1 type 2 xtbf#t 3-state output for high speed type 3 xtbf3at 3-state output for low noise type 3 xtbf3bt notes *1: the # denotes 1, or 2, with the i oh /i ol values corresponding to type 1, and type 2 respectively (for details, refer to table 4-3). *2: in addition to the configurations shown in table 4-10, the fail-safe output buffers may be configured without test pins. customers desiring to use such configurations should direct inquiries to epson. table 4-11 fail-safe bi-directional buffers list input level function i oh /i ol cell name *1, *2 bi-directional output type 1 type 2 xbb#t bi-directional output for high speed type 3 xbb3at cmos bi-directional output for low noise type 3 xbb3bt bi-directional output type 1 type 2 xbg#t bi-directional output for high speed type 3 xbg3at cmos schmitt bi-directional output for low noise type 3 xbg3bt notes *1: the # denotes 1, or 2, with the i oh /i ol values corresponding to type 1, and type 2, respectively (for details, refer to table 4-3). *2: in addition to the configurations shown in table 4-11, the fail-safe bi-directional buffers may be configured with pull-up/pull-down resistors or without test pins. customers desiring to use such configurations should direct inquiries to epson. chapter 4 types of input/output buffers and their use (x type) 36 epson embedded array S1X60000 series design guide 4.2.5 gated cells 4.2.5.1 overview the S1X60000 series (x type) gated i/o cell is the first product that allows inputs to pins to be placed in the floating, or high-z, state without the use of pull-up or pull-down circuits. moreover, the power supply on the high voltage side (hv dd ) in a dual power supply design can be cut off. there are two types of cells to choose from depending on whether a high level control signal or low level control signal shuts off the power supply. therefore, customers can choose the desired type of cell according to their circuit design. 4.2.5.2 features (1) the gated cells can be positioned as desired by customers. there are no limitations on the number of cells used or the locations in which they are placed. as a result, freedom of design is increased. (2) the power supply on the high voltage side (hv dd ) in a dual power supply design can be cut off. however, because special measures must be taken for this cut off, please contact the sales division of epson. (3) inputs can be placed in the high-z state without the use of pull-up or pull-down circuits. (4) due to circuit structure, the input level of the gated i/o cell in a dual power supply system is not hv dd system but lv dd system cmos level. (5) there are two types of cells to choose from depending on whether a high level control signal or low level control signal shuts off the power supply. (6) because the gated cells are completely cmos structured, the power consumption can be suppressed to a minimum. 4.2.5.3 usage precautions (1) to place inputs in the high-z state through the use of gated i/o cells, inputs to pins must be shut off by using gated i/o cell control signals before they enter the high-z state. if inputs are placed in the high-z state without performing this control, large current may flow into the cell as in ordinary cells, causing it to break down. conversely, the same problem may occur when using gated i/o cell control to connect inputs (in the high-z state) to pins. in such a case, the logic level latched into the device?s internal circuit cannot be guaranteed. (2) when the power supply on the high voltage side (hv dd ) is to be cut off by using a gated i/o cell, the same processing as described in (1) is required. this processing must be performed; otherwise, the logic level latched to the device?s internal circuit cannot be guaranteed. moreover, because special measures must be taken for cut-off, please contact the sales division of epson. chapter 4 types of input/output buffers and their use (x type) embedded array S1X60000 series epson 37 design guide 4.2.5.4 list of cells table 4-12 gated input buffers list cell name *1 input level whether pull-up/pull-down resistors are included xiba xibap# xibad# cmos (and type) none pull-up resistor included pull-down resistor included xibo xibop# xibod# cmos (or type) none pull-up resistor included pull-down resistor included notes *1: the # denotes 1 or 2, with the pull-up/pull-down resistance values corresponding to type 1 and type 2, respectively (for details, refer to table 4-1). table 4-13 gated bi-directional buffers list input level function i oh /i ol cell name *1, *2 bi-directional output type 1 type 2 type 3 xba#t bi-directional output for high speed type 3 xba3at and type bi-directional output for low noise type 3 xba3bt bi-directional output type 1 type 2 type 3 xbo#t bi-directional output for high speed type 3 xbo3at cmos or type bi-directional output for low noise type 3 xbo3bt notes *1: the # denotes 1, 2, or 3, with the i oh /i ol values corresponding to type 1, type 2, and type 3, respectively (for details, refer to table 4-3). *2: in addition to the configurations shown in table 4-13, the gated bi-directional buffers may be configured with pull-up/pull-down resistors or without test pins. customers desiring to use such configurations should direct inquiries to epson. chapter 4 types of input/output buffers and their use (x type) 38 epson embedded array S1X60000 series design guide 4.3 dual power supply input/output buffers if your system uses dual power supplies, use input/output buffers designed exclusively for operation with dual power supplies. (in this case, be careful not to use input/output buffers designed for operation with a single power supply.) moreover, input/output buffers for a single power supply system and those for a dual power supply system cannot be used in combination. however, the test buffer (xitst1) can be used in both single power supply and dual power supply systems. (combined use with the xf type of input/output buffers is also not allowed.) (1) hv dd input/output buffers the hv dd input/output buffers are available in several types. these include input buffers that accept as input 3.3 v signals, output buffers that output 3.3 v amplitude signals, and bi-directional buffers that accept as input 3.3 v signals or output 3.3 v amplitude signals. (2) lv dd input/output buffers the lv dd input/output buffers are available in several types. these include input buffers that accept as input 2.5 v (or 2.0 v) signals, output buffers that output 2.5 v (or 2.0 v) amplitude signals, and bi-directional buffers that accept as input 2.5 v (or 2.0 v) signals or output 2.5 v (or 2.0 v) amplitude signals. for lv dd bi-directional buffers, do not apply voltages above lv dd . this is due to the fact that, if hv dd signals are supplied to those buffers, an excessive current flows in their internal protective diode, causing their quality to degrade (in such a case, use the fail-safe cells described in section 4.3.4, ?fail-safe cells?). 4.3.1 input buffers (1) hv dd input buffers the input buffers are configured using only input cells. the hv dd input buffers consist of a first input stage configured with an hv dd input circuit and a next stage configured with an lv dd circuit, so that hv dd signals are converted into lv dd signals before being fed into the msi cell. table 4-15 lists the hv dd input buffers. table 4-14 rated pull-up/pull-down resistance values at each voltage type of pull-up/pull-down resistor resistance value (hv dd = 3.3 v) unit type 1 60 k ? type 2 120 k ? chapter 4 types of input/output buffers and their use (x type) embedded array S1X60000 series epson 39 design guide table 4-15 hv dd input buffers list cell name *1 input level whether pull-up/pull-down resistors are included xhibc xhibcp# xhibcd# cmos cmos cmos none pull-up resistor pull-down resistor xhibt xhibtp# xhibtd# lvttl lvttl lvttl none pull-up resistor pull-down resistor xhibh xhibhp# xhibhd# cmos schmitt cmos schmitt cmos schmitt none pull-up resistor pull-down resistor xhibs xhibsp# xhibsd# lvttl schmitt lvttl schmitt lvttl schmitt none pull-up resistor pull-down resistor xhibpb xhibpbp# xhibpbd# pci-3v pci-3v pci-3v none pull-up resistor pull-down resistor notes *1: the # denotes 1 or 2, with the pull-up/pull-down resistance values corresponding to type 1 and type 2, respectively (for details, refer to table 4-14). (2) lv dd input buffers the input buffers are configured using only input cells. table 4-17 lists the lv dd input buffers. table 4-16 rated pull-up/pull-down resistance values at each voltage resistance value type of pull-up/pull-down resistor lv dd = 2.5 v lv dd = 2.0 v unit type 1 50 70 k ? type 2 100 140 k ? table 4-17 lv dd input buffers list cell name *1 input level whether pull-up/pull-down resistors are included xlibc xlibcp# xlibcd# cmos cmos cmos none pull-up resistor pull-down resistor xlibh xlibhp# xlibhd# cmos schmitt cmos schmitt cmos schmitt none pull-up resistor pull-down resistor notes *1: the # denotes 1 or 2, with the pull-up/pull-down resistance values corresponding to type 1 and type 2, respectively (for details, refer to table 4-16). chapter 4 types of input/output buffers and their use (x type) 40 epson embedded array S1X60000 series design guide 4.3.2 output buffers (1) hv dd output buffers tables 4-19 and 4-21 list the hv dd output buffers. table 4-18 rated i oh and i ol values at each voltage type of output current i oh *1 /i ol *2 (hv dd = 3.3v) unit type s -0.1/0.1 ma type m -1/1 ma type 1 -3/3 ma type 2 -6/6 ma type 3 -12/12 ma note *1: v oh = hv dd - 0.4 v *2: v ol = 0.4 v table 4-19 hv dd output buffers list function i ol /i oh cell name *1, *2 normal output type s type m type 1 type 2 type 3 xhob#t normal output for high speed type 3 xhob3at normal output for low noise type 3 xhob3bt normal output fot pci pci-3v xhobpbt 3-state output type s type m type 1 type 2 type 3 xhtb#t 3-state output for high speed type 3 xhtb3at 3-state output for low noise type 3 xhtb3bt 3-state output fot pci pci-3v xhtbpbt 3-state output (bus hold circuit) type m type 1 type 2 type 3 xhtb$ht 3-state output for high speed (bus hold circuit) type 3 xhtb3aht 3-state output for low noise (bus hold circuit) type 3 xhtb3bht notes *1: note that # denotes s, m, 1, 2, or 3; $ denotes m, 1, 2, or 3 with their i oh /i ol values corresponding to type s, type m, type 1, type 2, and type 3, respectively (for details, refer to table 4-18). *2: in addition to the configurations shown in table 4-19, the output buffers may be configured without test pins. customers desiring to use such configurations should direct inquiries to epson. chapter 4 types of input/output buffers and their use (x type) embedded array S1X60000 series epson 41 design guide table 4-20 rated i ol values at each voltage type of output current i ol *1 (hv dd = 3.3v) unit type 1 3 ma type 2 6 ma type 3 12 ma note *1: v ol = 0.4 v table 4-21 hv dd n channel open drain output buffers list function i ol cell name *1, *2 normal output type 1 type 2 type 3 xhod#t notes *1: the # denotes 1, 2, or 3, with the i ol values corresponding to type 1, type 2, and type 3, respectively (for details, refer to table 4-20). *2: in addition to the configurations shown in table 4-21, the hv dd n channel open drain output buffers may be configured without test pins. customers desiring to use such configurations should direct inquiries to epson. chapter 4 types of input/output buffers and their use (x type) 42 epson embedded array S1X60000 series design guide (2) lv dd output buffers tables 4-23 and 4-25 list the lv dd output buffers. table 4-22 rated i oh and i ol values at each voltage i oh *1 /i ol *2 type of output current lv dd = 2.5 v lv dd = 2.0 v unit type s -0.1/0.1 -0.05/0.05 ma type m -1/1 -0.3/0.3 ma type 1 -3/3 -1/1 ma type 2 -6/6 -2/2 ma type 3 -9/9 -3/3 ma notes *1: v oh = lv dd - 0.4 v (lv dd = 2.5 v) or lv dd - 0.2 v (lv dd = 2.0 v) *2: v ol = 0.4 v (lv dd = 2.5 v) or 0.2 v (lv dd = 2.0 v) table 4-23 lv dd output buffers list function i oh /i ol cell name *1, *2 normal output type s type m type 1 type 2 type 3 xlob#t normal output for high speed type 3 xlob3at normal output for low noise type 3 xlob3bt 3-state output type s type m type 1 type 2 type 3 xltb#t 3-state output for high speed type 3 xltb3at 3-state output for low noise type 3 xltb3bt 3-state output (bus hold circuit) type m type 1 type 2 type 3 xltb$ht 3-state output for high speed (bus hold circuit) type 3 xltb3aht 3-state output for low noise (bus hold circuit) type 3 xltb3bht notes *1: note that # denotes s, m, 1, 2, or 3; $ denotes m, 1, 2, or 3 with their i oh /i ol values corresponding to type s, type m, type 1, type 2, and type 3, respectively (for details, refer to table 4-22). *2: in addition to the configurations shown in table 4-23, the output buffers may be configured without test pins. customers desiring to use such configurations should direct inquiries to epson. chapter 4 types of input/output buffers and their use (x type) embedded array S1X60000 series epson 43 design guide table 4-24 rated i ol values at each voltage i ol *1 type of output current lv dd = 2.5 v lv dd = 2.0 v unit type 1 3 1 ma type 2 6 2 ma type 3 9 3 ma note *1: v ol = 0.4 v (lv dd = 2.5 v) or 0.2 v (lv dd = 2.0 v) table 4-25 lv dd n channel open drain output buffers list function i ol cell name *1, *2 normal output type 1 type 2 type 3 xlod#t notes *1: the # denotes 1, 2, or 3, with the i ol values corresponding to type 1, type 2, and type 3, respectively (for details, refer to table 4-24). *2: in addition to the configurations shown in table 4-25, the n channel open drain output buffers may be configured without test pins. customers desiring to use such configurations should direct inquiries to epson. chapter 4 types of input/output buffers and their use (x type) 44 epson embedded array S1X60000 series design guide 4.3.3 bi-directional buffers (1) hv dd bi-directional buffers tables 4-26 and 4-27 list the hv dd bi-directional buffers. table 4-26 hv dd bi-directional buffers list (1/2) input level function i oh /i ol cell name *1, *2 bi-directional output type s type m type 1 type 2 type 3 xhbt#t bi-directional output for high speed type 3 xhbt3at lvttl bi-directional output for low noise type 3 xhbt3bt bi-directional output type s type m type 1 type 2 type 3 xhbc#t bi-directional output for high speed type 3 xhbc3at cmos bi-directional output for low noise type 3 xhbc3bt pci bi-directional output for pci pci-3v xhbpbt bi-directional type s type m type 1 type 2 type 3 xhbs#t bi-directional output for high speed type 3 xhbs3at lvttl schmitt bi-directional output for low noise type 3 xhbs3bt bi-directional type s type m type 1 type 2 type 3 xhbh#t bi-directional output for high speed type 3 xhbh3at cmos schmitt bi-directional output for low noise type 3 xhbh3bt notes *1: note that # denotes s, m, 1, 2, or 3; $ denotes m, 1, 2, or 3 with their i oh /i ol values corresponding to type s, type m, type 1, type 2, and type 3, respectively (for details, refer to table 4-18). *2: in addition to the configurations shown in table 4-26, the hv dd bi-directional buffers may be configured with pull-up/pull-down resistors or without test pins. customers desiring to use such configurations should direct inquiries to epson. chapter 4 types of input/output buffers and their use (x type) embedded array S1X60000 series epson 45 design guide table 4-26 list of hv dd bi-directional buffers list (2/2) input level function i oh /i ol cell name *1, *2 bi-directional output (bus hold circuit) type m type 1 type 2 type 3 xhbt#ht bi-directional output for high speed (bus hold circuit) type 3 xhbt3aht lvttl bi-directional output for low noise (bus hold circuit) type 3 xhbt3bht bi-directional output (bus hold circuit) type m type 1 type 2 type 3 xhbc#ht bi-directional output for high speed (bus hold circuit) type 3 xhbc3aht cmos bi-directional output for low noise (bus hold circuit) type 3 xhbc3bht bi-directional output (bus hold circuit) type m type 1 type 2 type 3 xhbs#ht bi-directional output for high speed (bus hold circuit) type 3 xhbs3aht lvttl schmitt bi-directional output for low noise (bus hold circuit) type 3 xhbs3bht bi-directional output (bus hold circuit) type m type 1 type 2 type 3 xhbh#ht bi-directional output for high speed (bus hold circuit) type 3 xhbh3aht cmos schmitt bi-directional output for low noise (bus hold circuit) type 3 xhbh3bht notes *1: note that # denotes s, m, 1, 2, or 3; $ denotes m, 1, 2, or 3 with their i oh /i ol values corresponding to type s, type m, type 1, type 2, and type 3, respectively (for details, refer to table 4-18). *2: in addition to the configurations shown in table 4-26, the hv dd bi-directional buffers may be configured with pull-up/pull-down resistors or without test pins. customers desiring to use such configurations should direct inquiries to epson. chapter 4 types of input/output buffers and their use (x type) 46 epson embedded array S1X60000 series design guide table 4-27 hv dd n channel open drain bi-directional buffers list input level function i ol cell name *1, *2 lvttl bi-directional output type 1 type 2 type 3 xhbdt#t cmos bi-directional output type 1 type 2 type 3 xhbdc#t lvttl schmitt bi-directional output type 1 type 2 type 3 xhbds#t cmos schmitt bi-directional output type 1 type 2 type 3 xhbdh#t notes *1: the # denotes 1, 2, or 3, with the i ol values corresponding to type 1, type 2, and type 3, respectively (for details, refer to table 4-20). *2: in addition to the configurations shown in table 4-27, the hv dd n channel open drain bi-directional buffers may be configured without test pins. customers desiring to use such configurations should direct inquiries to epson. chapter 4 types of input/output buffers and their use (x type) embedded array S1X60000 series epson 47 design guide (2) lv dd bi-directional buffers tables 4-28 and 4-29 list the lv dd bi-directional buffers. table 4-28 lv dd bi-directional buffers list input level function i oh /i ol cell name *1, *2 bi-directional output type s type m type 1 type 2 type 3 xlbc#t bi-directional output for high speed type 3 xlbc3at cmos bi-directional output for low noise type 3 xlbc3bt bi-directional output type s type m type 1 type 2 type 3 xlbh#t bi-directional output for high speed type 3 xlbh3at cmos schmitt bi-directional output for low noise type 3 xlbh3bt bi-directional output (bus hold circuit) type m type 1 type 2 type 3 xlbc$ht bi-directional output for high speed (bus hold circuit) type 3 xlbc3aht cmos bi-directional output for low noise (bus hold circuit) type 3 xlbc3bht bi-directional output (bus hold circuit) type m type 1 type 2 type 3 xlbh$ht bi-directional output for high speed (bus hold circuit) type 3 xlbh3aht cmos schmitt bi-directional output for low noise (bus hold circuit) type 3 xlbh3bht notes *1: note that # denotes s, m, 1, 2, or 3; $ denotes m, 1, 2, or 3 with their i oh /i ol values corresponding to type s, type m, type 1, type 2, and type 3, respectively (for details, refer to table 4-22). *2: in addition to the configurations shown in table 4-28, the bi-directional buffers may be configured with pull-up/pull-down resistors or without test pins. customers desiring to use such configurations should direct inquiries to epson. chapter 4 types of input/output buffers and their use (x type) 48 epson embedded array S1X60000 series design guide table 4-29 lv dd n channel open drain bi-directional buffers list input level function i ol cell name *1, *2 cmos bi-directional output type 1 type 2 type 3 xlbdc#t cmos schmitt bi-directional output type 1 type 2 type 3 xlbdh#t notes *1: the # denotes 1, 2, or 3, with the i ol values corresponding to type 1, type 2, and type 3, respectively (for details, refer to table 4-24). *2: in addition to the configurations shown in table 4-29, the n channel open drain bi-directional buffers may be configured without test pins. customers desiring to use such configurations should direct inquiries to epson. chapter 4 types of input/output buffers and their use (x type) embedded array S1X60000 series epson 49 design guide 4.3.4 fail-safe cells 4.3.4.1 overview the dual power supply fail-safe cells are outlined in section 4.2.4.1, ?overview? (the fail-safe cells used in the dual power supply specification are lv dd cells). 4.3.4.2 features for the features of the dual power supply fail-safe cells, refer to section 4.2.4.2, ?features.? 4.3.4.3 usage precautions for precautions to be taken when dual power supply fail-safe cells are used, refer to section 4.2.4.3, ?usage precautions.? 4.3.4.4 list of cells table 4-30 fail-safe input buffers list cell name *1 input level whether pull-up resistors are included xlibbp# cmos pull-up resistors xlibgp# cmos schmitt pull-up resistors notes *1: the # denotes 1 or 2, with the pull-up resistance values corresponding to type 1 and type 2, respectively (for details, refer to table 4-16). table 4-31 fail-safe output buffers list function i oh /i ol cell name *1, *2 3-state output type 1 type 2 xltbf#t 3-state output for high speed type 3a xltbf3at 3-state output for low noise type 3b xltbf3bt notes *1: the # denotes 1, or 2, with the i oh /i ol values corresponding to type 1, and type 2, respectively (for details, refer to table 4-22). *2: in addition to the configurations shown in table 4-31, the fail-safe output buffers may be configured without test pins. customers desiring to use such configurations should direct inquiries to epson. chapter 4 types of input/output buffers and their use (x type) 50 epson embedded array S1X60000 series design guide table 4-32 fail-safe bi-directional buffers list input level function i oh /i ol cell name *1, *2 bi-directional output type 1 type 2 xlbb#t bi-directional output for high speed type 3 xlbb3at cmos bi-directional output for low noise type 3 xlbb3bt bi-directional output type 1 type 2 xlbg#t bi-directional output for high speed type 3 xlbg3at cmos schmitt bi-directional output for low noise type 3 xlbg3bt notes *1: the # denotes 1, or 2, with the i oh /i ol values corresponding to type 1, and type 2, respectively (for details, refer to table 4-22). *2: in addition to the configurations shown in table 4-32, the fail-safe bi-directional buffers may be configures with pull-up/pull-down resistors or without test pins. customers desiring to use such configurations should direct inquiries to epson. chapter 4 types of input/output buffers and their use (x type) embedded array S1X60000 series epson 51 design guide 4.3.5 gated cells 4.3.5.1 overview the dual power supply gated cells are outlined in section 4.2.5.1, ?overview.? (the gated cells for the dual power supply specification are hv dd cells.) 4.3.5.2 features for the features of the dual power supply gated cells, refer to section 4.2.5.2, ?features.? 4.3.5.3 usage precautions for the precautions to be taken when dual power supply gated cells are used, refer to section 4.2.5.3, ?usage precautions.? 4.3.5.4 list of cells table 4-33 gated cell input buffers list cell name *1, *2 input level whether pull-up/pull-down resistors are xhiba xhibap# xhibad# cmos (and type) none pull-up resistor pull-down resistor xhibo xhibop# xhibod# cmos (or type) none pull-up resistor pull-down resistor notes *1: the # denotes 1 or 2, with the pull-up/pull-down resistance values corresponding to type 1 and type 2, respectively (for details, refer to table 4-14). table 4-34 gated cell bi-directional buffers list input level function i oh /i ol cell name *1, *2 bi-directional output type 1 type 2 type 3 xhba#t bi-directional output for high speed type 3 xhba3at and type bi-directional output for low noise type 3 xhba3bt bi-directional output type 1 type 2 type 3 xhbo#t bi-directional output for high speed type 3 xhbo3at cmos or type bi-directional output for low noise type 3 xhbo3bt notes *1: the # denotes 1, 2, or 3, with the i oh /i ol values corresponding to type 1, type 2, and type 3, respectively (for details, refer to table 4-18). *2: in addition to the configurations shown in table 4-34, the gated bi-directional buffers may be configured with pull-up/pull-down resistors or without test pins. customers desiring to use such configurations should direct inquiries to epson. chapter 4 types of input/output buffers and their use (x type) 52 epson embedded array S1X60000 series design guide 4.4 dual power supplies guidelines the S1X60000 series allows each input/output buffer to be interfaced with 3.3 v, 2.5 v, or 2.0 v signals as desired, using a dual power supply system. the internal cell area operates using a 2.5 v or 2.0 v single power supply. 4.4.1 method of adapting to dual power supplies the S1X60000 series allows input/output buffers to be interfaced with the signals of voltages that differ from the internal operating voltage. there are two methods for interfacing with different power supply voltages. ? for a single power supply in a single power supply system, it is possible to apply input signals of voltages higher than the power supply voltage, using n channel open drain type buffers or fail-safe cells. however, high voltage signals above the power supply voltage cannot be output. this problem can be solved through the combined use of n channel open drain type buffers and external pull-up resistors. ? for dual power supplies by using input buffers designed exclusively for operation with dual power supplies, it is possible to apply input signals of voltages higher than the internal operating voltage. similarly, high voltage signals above the internal operating voltage can be output using dual power supply output buffers. 4.4.2 power supplies for dual power operation if your circuit is to be operated using two different power supplies, use two power supply cells: hv dd and lv dd . specifically, hv dd may be used for hv dd input/output buffers, and lv dd may be used for lv dd input/output buffers and internal cells. the power supply voltages must always satisfy the equation below. hv dd lv dd if hv dd < lv dd , operation of the internal circuit cannot be guaranteed. the operating conditions specified below are recommended. hv dd = 3.3 v, lv dd = 2.5 v hv dd = 3.3 v, lv dd = 2.0 v 4.4.3 turning on/off dual power supplies for chips designed to dual power supply specifications, make sure the power is turned on and off in the order specified below. when turning on: lv dd (internal) hv dd (i/o section) input signals applied when turning off: input signals off hv dd (i/o section) lv dd (internal) note 1: avoid keeping only hv dd turned on (for 1 sec or more) while lv dd is turned off, so as not to degrade the chip?s reliability. note 2: when turning hv dd back on after it was off, always be sure to initialize the circuit following power on. this is necessary to ensure the internal circuit state in the event of power supply noise or the like. chapter 5 types of input/output buffers and their use (xf type) embedded array S1X60000 series epson 53 design guide chapter 5 types of input/output buffers and their use (xf type) this chapter describes in detail how the input buffers, output buffers, and bi-directional buffers of the six6000 series (xf type) are constructed. 5.1 types of input/output buffers the S1X60000 series (xf type) offers a wide selection of cells to choose from depending on the input interface level, whether schmitt trigger input is needed and pull-up/pull-down resistors are included, output drive capability, and whether noise reduction measures are incorporated. choose the input/output buffers that best suit your system by considering the items described below. note that input/output buffers of this type can only be used with dual power supplies (3.3 v/2.5 v or 3.3 v/2.0 v). 5.1.1 selecting input/output buffers (1) selecting an input buffer a) whether 5 v interfacing is needed b) whether the necessary interface level is cmos level or lvttl level c) whether schmitt trigger input is needed (i.e., whether hysteresis characteristics are required) d) whether internal pull-up/pull-down resistors are needed (2) selecting an output buffer a) whether 5 v pull-up resisters external to the chip are needed b) necessary amounts of output drive currents (i ol /i oh ) c) whether noise reduction measures are needed d) whether a bus hold circuit is needed (3) selecting a bi-directional buffer consider items (1) and (2) above to select a bi-directional buffer. ? input interface level (1) when hv dd = 3.3 v input level lvttl level, cmos level, lvttl schmitt, cmos schmitt, pci-3v* output level cmos level, pci-3v* chapter 5 types of input/output buffers and their use (xf type) 54 epson embedded array S1X60000 series design guide (2) when lv dd = 2.5 v input level cmos level, cmos schmitt output level cmos level (3) when lv dd = 2.0 v input level cmos level, cmos schmitt output level cmos level note: * for the pci interface, please contact the sales division of epson. ? output drive capability see tables 1-13, 1-14, and 1-15 for electrical characteristics. ? pull-up/pull-down resistors see tables 1-13, 1-14, and 1-15 for electrical characteristics. 5.1.2 bus hold circuit to ensure that the output pins and bi-directional pins will not enter a high-impedance state, the S1X60000 series (xf type) has available an input/output buffer that comes equipped with a bus hold facility to hold the data at the output pins. however, because the bus hold circuit?s retention capability is suppressed so as not to adversely affect the ordinary operation of the cell, do not use the output data held by the circuit as valid data. the retained data may easily change state when any data is supplied from an external circuit. for the bus hold circuit?s output retention current, refer to table 1-13 through 1-15. chapter 5 types of input/output buffers and their use (xf type) embedded array S1X60000 series epson 55 design guide 5.2 dual power supply input/output buffers the input/output buffers of the S1X60000 series (xf type) can only be used in a dual power supply system. (these buffers cannot be used in combination with the x type of input/output buffers.) (1) hv dd input/output buffers the hv dd input/output buffers are available in several types. these include input buffers that accept as input 3.3 v signals, output buffers that output 3.3 v amplitude signals, and bi-directional buffers that accept as input 3.3 v signals or output 3.3 v amplitude signals. moreover, 5 v tolerant fail-safe cells are available, which allow 5.0 v amplitude signals to be applied. (2) lv dd input/output buffers the lv dd input/output buffers are available in several types. these include input buffers that accept as input 2.5 v (or 2.0 v) signals, output buffers that output 2.5 v (or 2.0 v) amplitude signals, and bi-directional buffers that accept as input 2.5 v (or 2.0 v) signals or output 2.5 v (or 2.0 v) amplitude signals. for lv dd bi-directional buffers, do not apply voltages above lv dd . this is due to the fact that, if hv dd signals are supplied to those buffers, an excessive current flows in their internal protective diode, causing their quality to degrade (in such a case, use the fail-safe cells described in section 5.2.4, ?fail-safe cells?). 5.2.1 input buffers (1) hv dd input buffers the input buffers are configured using only input cells. the hv dd input buffers consist of a first input stage configured with an hv dd input circuit and a next stage configured with an lv dd circuit, so that hv dd signals are converted into lv dd signals before being fed into the msi cell (internal cell area). table 5-2 lists the hv dd input buffers. table 5-1 rated pull-up/pull-down-resistance values at each voltage type of pull-up/pull-down resistor resistance value (hv dd = 3.3 v) unit type 1 60 k ? type 2 120 k ? chapter 5 types of input/output buffers and their use (xf type) 56 epson embedded array S1X60000 series design guide table 5-2 hv dd input buffers list cell name *1 input level whether pull-up/pull-down resistors are included xfhibc xfhibcp# xfhibcd# cmos cmos cmos none pull-up resistor pull-down resistor xfhibt xfhibtp# xfhibtd# lvttl lvttl lvttl none pull-up resistor pull-down resistor xfhibh xfhibhp# xfhibhd# cmos schmitt cmos schmitt cmos schmitt none pull-up resistor pull-down resistor xfhibs xfhibsp# xfhibsd# lvttl schmitt lvttl schmitt lvttl schmitt none pull-up resistor pull-down resistor xfhibpb xfhibpbp# xfhibpbd# pci-3v pci-3v pci-3v none pull-up resistor pull-down resistor notes *1: the # denotes 1 or 2, with the pull-up/pull-down resistance values corresponding to type 1 and type 2, respectively (for details, refer to table 5-1). (2) lv dd input buffers the input buffers are configured using only input cells. table 5-4 lists the lv dd input buffers. table 5-3 rated pull-up/pull-down resistance values at each voltage resistance value type of pull-up/pull-down resistor lv dd = 2.5 v lv dd = 2.0 v unit type 1 50 70 k ? type 2 100 140 k ? table 5-4 lv dd input buffers list cell name *1 input level whether pull-up/pull-down resistors are included xflibc xflibcp# xflibcd# cmos cmos cmos none pull-up resistor pull-down resistor xflibh xflibhp# xflibhd# cmos schmitt cmos schmitt cmos schmitt none pull-up resistor pull-down resistor notes *1: the # denotes 1 or 2, with the pull-up/pull-down resistance values corresponding to type 1 and type 2, respectively (for details, refer to table 5-3). chapter 5 types of input/output buffers and their use (xf type) embedded array S1X60000 series epson 57 design guide 5.2.2 output buffers (1) hv dd output buffers tables 5-6 and 5-8 list the hv dd output buffers. table 5-5 rated i oh and i ol values at each voltage type of output current i oh *1 /i ol *2 (hv dd = 3.3v) unit type s -0.1/0.1 ma type m -1/1 ma type 1 -3/3 ma type 2 -6/6 ma type 3 -12/12 ma note *1: v oh = hv dd - 0.4 v *2: v ol = 0.4 v table 5-6 hv dd output buffers list function i ol /i oh cell name *1, *2 normal output type s type m type 1 type 2 type 3 xfhob#t normal output for high speed type 3 xfhob3at normal output for low noise type 3 xfhob3bt normal output fot pci pci-3v xfhobpbt 3-state output type s type m type 1 type 2 type 3 xfhtb#t 3-state output for high speed type 3 xfhtb3at 3-state output for low noise type 3 xfhtb3bt 3-state output fot pci pci-3v xfhtbpbt 3-state output (bus hold circuit) type m type 1 type 2 type 3 xfhtb$ht 3-state output for high speed (bus hold circuit) type 3 xfhtb3aht 3-state output for low noise (bus hold circuit) type 3 xfhtb3bht notes *1: note that # denotes s, m, 1, 2, or 3; $ denotes m, 1, 2, or 3 with their i oh /i ol values corresponding to type s, type m, type 1, type 2, and type 3, respectively (for details, refer to table 5-5). *2: in addition to the configurations shown in table 5-6, the hv dd output buffers may be configured without test pins. customers desiring to use such configurations should direct inquiries to epson. chapter 5 types of input/output buffers and their use (xf type) 58 epson embedded array S1X60000 series design guide table 5-7 rated i ol values at each voltage type of output current i ol *1 (hv dd = 3.3v) unit type 1 3 ma type 2 6 ma type 3 12 ma note *1: v ol = 0.4 v table 5-8 hv dd n channel open drain output buffers list function i ol cell name *1, *2 normal output type 1 type 2 type 3 xfhod#t notes *1: the # denotes 1, 2, or 3, with the i ol values corresponding to type 1, type 2, and type 3, respectively (for details, refer to table 5-7). *2: in addition to the configurations shown in table 5-8, the hv dd n channel open drain output buffers may be configured without test pins. customers desiring to use such configurations should direct inquiries to epson. chapter 5 types of input/output buffers and their use (xf type) embedded array S1X60000 series epson 59 design guide (2) lv dd output buffers tables 5-10 and 5-12 list the lv dd output buffers. table 5-9 rated i oh and i ol values at each voltage i oh *1 /i ol *2 type of output current lv dd = 2.5 v lv dd = 2.0 v unit type s -0.1/0.1 -0.05/0.05 ma type m -1/1 -0.3/0.3 ma type 1 -3/3 -1/1 ma type 2 -6/6 -2/2 ma type 3 -9/9 -3/3 ma notes *1: v oh = lv dd - 0.4 v (lv dd = 2.5 v) or lv dd - 0.2 v (lv dd = 2.0 v) *2: v ol = 0.4 v (lv dd = 2.5 v) or 0.2 v (lv dd = 2.0 v) table 5-10 lv dd output buffers list function i oh /i ol cell name *1, *2 normal output type s type m type 1 type 2 type 3 xflob#t normal output for high speed type 3 xflob3at normal output for low noise type 3 xflob3bt 3-state output type s type m type 1 type 2 type 3 xfltb#t 3-state output for high speed type 3 xfltb3at 3-state output for low noise type 3 xfltb3bt 3-state output (bus hold circuit) type m type 1 type 2 type 3 xfltb$ht 3-state output for high speed (bus hold circuit) type 3 xfltb3aht 3-state output for low noise (bus hold circuit) type 3 xfltb3bht notes *1: note that # denotes s, m, 1, 2, or 3; $ denotes m, 1, 2, or 3 with their i oh /i ol values corresponding to type s, type m, type 1, type 2, and type 3, respectively (for details, refer to table 5-9). *2: in addition to the configurations shown in table 5-10, output buffers may be configured without test pins. customers desiring to use such configurations should direct inquiries to epson. chapter 5 types of input/output buffers and their use (xf type) 60 epson embedded array S1X60000 series design guide table 5-11 rated i ol values at each voltage i ol *1 type of output current lv dd = 2.5 v lv dd = 2.0 v unit type 1 3 1 ma type 2 6 2 ma type 3 9 3 ma note *1: v ol = 0.4 v (lv dd = 2.5 v) or 0.2 v (lv dd = 2.0 v) table 5-12 lv dd n channel open drain output buffers list function i ol cell name *1, *2 normal output type 1 type 2 type 3 xflod#t notes *1: the # denotes 1, 2, or 3, with the i ol values corresponding to type 1, type 2, and type 3, respectively (for details, refer to table 5-11). *2: in addition to the configurations shown in table 5-12, the lv dd n channel open drain output buffers may be configured without test pins. customers desiring to use such configurations should direct inquiries to epson. chapter 5 types of input/output buffers and their use (xf type) embedded array S1X60000 series epson 61 design guide 5.2.3 bi-directional buffers (1) hv dd bi-directional buffers tables 5-13 and 5-14 list the hv dd bi-directional buffers. table 5-13 hv dd bi-directional buffers list (1/2) input level function i oh /i ol cell name *1, *2 bi-directional output type s type m type 1 type 2 type 3 xfhbt#t bi-directional output for high speed type 3 xfhbt3at lvttl bi-directional output for low noise type 3 xfhbt3bt bi-directional output type s type m type 1 type 2 type 3 xfhbc#t bi-directional output for high speed type 3 xfhbc3at cmos bi-directional output for low noise type 3 xfhbc3bt pci bi-directional output for pci pci-3v xfhbpbt bi-directional type s type m type 1 type 2 type 3 xfhbs#t bi-directional output for high speed type 3 xfhbs3at lvttl schmitt bi-directional output for low noise type 3 xfhbs3bt bi-directional type s type m type 1 type 2 type 3 xfhbh#t bi-directional output for high speed type 3 xfhbh3at cmos schmitt bi-directional output for low noise type 3 xfhbh3bt notes *1: the # denotes 1, 2, or 3, with the i oh /i ol values corresponding to type s, type m, type 1, type 2, and type 3, respectively (for details, refer to table 5-5). *2: in addition to the configurations shown in table 5-13, the hv dd bi-directional buffers may be configured with pull-up/pull-down resistors or without test pins. customers desiring to use such configurations should direct inquiries to epson. chapter 5 types of input/output buffers and their use (xf type) 62 epson embedded array S1X60000 series design guide table 5-13 list of hv dd bi-directional buffers list (2/2) input level function i oh /i ol cell name *1, *2 bi-directional output (bus hold circuit) type m type 1 type 2 type 3 xfhbt#ht bi-directional output for high speed (bus hold circuit) type 3 xfhbt3aht lvttl bi-directional output for low noise (bus hold circuit) type 3 xfhbt3bht bi-directional output (bus hold circuit) type m type 1 type 2 type 3 xfhbc#ht bi-directional output for high speed (bus hold circuit) type 3 xfhbc3aht cmos bi-directional output for low noise (bus hold circuit) type 3 xfhbc3bht bi-directional output (bus hold circuit) type m type 1 type 2 type 3 xfhbs#ht bi-directional output for high speed (bus hold circuit) type 3 xfhbs3aht lvttl schmitt bi-directional output for low noise (bus hold circuit) type 3 xfhbs3bht bi-directional output (bus hold circuit) type m type 1 type 2 type 3 xfhbh#ht bi-directional output for high speed (bus hold circuit) type 3 xfhbh3aht cmos schmitt bi-directional output for low noise (bus hold circuit) type 3 xfhbh3bht notes *1: the # denotes 1, 2, or 3, with the i oh /i ol values corresponding to type m, type 1, type 2, and type 3, respectively (for details, refer to table 5-5). *2: in addition to the configurations shown in table 5-13, the hv dd bi-directional buffers may be configured with pull-up/pull-down resistors or without test pins. customers desiring to use such configurations should direct inquiries to epson. chapter 5 types of input/output buffers and their use (xf type) embedded array S1X60000 series epson 63 design guide table 5-14 hv dd n channel open drain bi-directional buffers list input level function i ol cell name *1, *2 lvttl bi-directional output type 1 type 2 type 3 xfhbdt#t cmos bi-directional output type 1 type 2 type 3 xfhbdc#t lvttl schmitt bi-directional output type 1 type 2 type 3 xfhbds#t cmos schmitt bi-directional output type 1 type 2 type 3 xfhbdh#t notes *1: the # denotes 1, 2, or 3, with the i ol values corresponding to type 1, type 2, and type 3, respectively (for details, refer to table 5-7). *2: in addition to the configurations shown in table 5-14, the hv dd n channel open drain bi-directional buffers may be configured without test pins. customers desiring to use such configurations should direct inquiries to epson. chapter 5 types of input/output buffers and their use (xf type) 64 epson embedded array S1X60000 series design guide (2) lv dd bi-directional buffers tables 5-15 and 5-16 list the lv dd bi-directional buffers. table 5-15 lv dd bi-directional buffers list input level function i oh /i ol cell name *1, *2 bi-directional output type s type m type 1 type 2 type 3 xflbc#t bi-directional output for high speed type 3 xflbc3at cmos bi-directional output for low noise type 3 xflbc3bt bi-directional output type s type m type 1 type 2 type 3 xflbh#t bi-directional output for high speed type 3 xflbh3at cmos schmitt bi-directional output for low noise type 3 xflbh3bt bi-directional output (bus hold circuit) type m type 1 type 2 type 3 xflbc$ht bi-directional output for high speed (bus hold circuit) type 3 xflbc3aht cmos bi-directional output for low noise (bus hold circuit) type 3 xflbc3bht bi-directional output (bus hold circuit) type m type 1 type 2 type 3 xflbh$ht bi-directional output for high speed (bus hold circuit) type 3 xflbh3aht cmos schmitt bi-directional output for low noise (bus hold circuit) type 3 xflbh3bht notes *1: note that # denotes s, m, 1, 2, or 3; $ denotes m, 1, 2, or 3 with their i oh /i ol values corresponding to type s, type m, type 1, type 2, and type 3, respectively (for details, refer to table 5-9). *2: in addition to the configurations shown in table 5-15, the lv dd bi-directional buffers may be configured with pull-up/pull-down resistors or without test pins. customers desiring to use such configurations should direct inquiries to epson. chapter 5 types of input/output buffers and their use (xf type) embedded array S1X60000 series epson 65 design guide table 5-16 lv dd n channel open drain bi-directional buffers list input level function i ol cell name *1, *2 cmos bi-directional output type 1 type 2 type 3 xflbdc#t cmos schmitt bi-directional output type 1 type 2 type 3 xflbdh#t notes *1: the # denotes 1, 2, or 3, with the i ol values corresponding to type 1, type 2, and type 3, respectively (for details, refer to table 5-11). *2: in addition to the configurations shown in table 5-16, the lv dd n channel open drain bi-directional buffers may be configured without test pins. customers desiring to use such configurations should direct inquiries to epson. chapter 5 types of input/output buffers and their use (xf type) 66 epson embedded array S1X60000 series design guide 5.2.4 fail-safe cells 5.2.4.1 overview the S1X60000 series (xf type) fail-safe cells allow signals above the power supply voltage to be interfaced, even while power is supplied. furthermore, no leakage current flows in those cells, despite the fact that the signals are interfaced while the power is cut off. therefore, they provide greater freedom of design than ever before. (these cells are used as lv dd system cells.) 5.2.4.2 features (1) the fail-safe cells can be positioned as desired by customers. there are no limitations on the number of cells that can be used or the locations in which they can be placed. (2) even when input signals above the power supply voltage are applied while power is supplied, no input leakage current flows. (for input buffers or bi-directional buffers with pull-up resistors, however, a small input leakage current of approximately 30 a may flow due to their circuit configuration.) (3) even when input signals are applied from the outside while the power is cut off, no input leakage current flows. (4) fail-safe cells with two different input levels, the cmos level and the cmos schmitt level, are available. (5) because the fail-safe cells are completely cmos structured, the power consumption can be suppressed to a minimum. 5.2.4.3 usage precautions (1) about input i/o cells ? for input buffers without resistors or with pull-down resistors, ordinary input buffers may be used directly as fail-safe cells. ? if input buffers with pull-up resistors are needed, always be sure to use fail-safe cells (however, a small input leakage current of approximately 30 a may flow due to their circuit configuration). (2) about output i/o cells ? provided that the output buffers are placed in high-z state or the bi-directional buffers are placed in input mode, no input leakage current may flow even when input signals above the power supply voltage are applied while power is supplied. ? if signals above the power supply voltage are applied while the bi-directional buffers are placed in output mode, an input leakage current flows as in ordinary input/output buffers. the same applies when pull-up resistors above the power supply voltage exist outside the chip. (if a high logic level above the power supply voltage is needed, use open drain type input/output buffers, with pull-up resistors added external to the chip in order to pull up the logic level high.) chapter 5 types of input/output buffers and their use (xf type) embedded array S1X60000 series epson 67 design guide (3) although the fail-safe cells can receive high voltage signals above the lsi?s operating voltage, be aware that the signal voltages applied to the fail-safe cells must never exceed their rated maximum voltage. 5.2.4.4 list of cells table 5-17 fail-safe input buffers list cell name *1 input level whether pull-up resistors are included xflibbp# cmos pull-up resistor included xflibgp# cmos schmitt pull-up resistor included notes *1: the # denotes 1 or 2, with the pull-up resistance values corresponding to type 1 and type 2, respectively (for details, refer to table 5-3). table 5-18 fail-safe output buffers list function i oh /i ol cell name *1, *2 3-state output type 1 type 2 xfltbf#t 3-state output for high speed type 3 xfltbf3at 3-state output for low noise type 3 xfltbf3bt notes *1: the # denotes 1, 2, 3, or 4, with the i oh /i ol values corresponding to type 1, type 2, type 3, and type 4, respectively (for details, refer to table 5-9). *2: in addition to the configurations shown in table 5-18, the fail-safe output buffers may be configured without test pins. customers desiring to use such configurations should direct inquiries to epson. table 5-19 fail-safe bi-directional buffers list input level function i oh /i ol cell name *1, *2 bi-directional output type 1 type 2 xflbb#t bi-directional output for high speed type 3 xflbb3at cmos bi-directional output for low noise type 3 xflbb3bt bi-directional output type 1 type 2 xflbg#t bi-directional output for high speed type 3 xflbg3at cmos schmitt bi-directional output for low noise type 3 xflbg3bt notes *1: the # denotes 1, or 2, with the i oh /i ol values corresponding to type 1, and type 2, respectively (for details, refer to table 5-9). *2: in addition to the configurations shown in table 5-19, the fail-safe bi-directional buffers may be configured with pull-up/pull-down resistors or without test pins. customers desiring to use such configurations should direct inquiries to epson. chapter 5 types of input/output buffers and their use (xf type) 68 epson embedded array S1X60000 series design guide 5.2.5 gated cells 5.2.5.1 overview the S1X60000 series (xf type) gated i/o cell is the first product that allows inputs to pins to be placed in the floating, or high-z, state without the use of pull-up or pull-down circuits. moreover, the power supply on the high voltage side (hv dd ) can be cut off. there are two types of cells to choose from depending on whether a high-level control signal or low-level control signal shuts off the power supply. therefore, customers can choose the desired type of cell according to their circuit design. (these cells are used as hv dd system cells.) 5.2.5.2 features (1) the gated cells can be positioned as desired by customers. there are no limitations on the number of cells used or the locations in which they are placed. as a result, freedom of design is increased. (2) it is also possible to cut off the power supply on the high- voltage side (hv dd ). however, because special measures must be taken for cut-off, please contact the sales division of epson. (3) inputs can be placed in high-z state without the use of pull-up or pull-down circuits. (4) due to circuit structure, the input level of the gated i/o cell is not hv dd system but lv dd system cmos level. (5) there are two types of cells to choose from depending on whether a high-level control signal or low-level control signal shuts off the power supply. (6) because the gated cells are completely cmos structured, the power consumption can be suppressed to a minimum. 5.2.5.3 usage precautions (1) to place inputs in the high-z state through the use of gated i/o cells, inputs to pins must be shut off by using gated i/o cell control signals before they enter the high-z state. if inputs are placed in the high-z state without performing this control, large current may flow into the cell as in ordinary cells, causing it to break down. conversely, the same problem may occur when using gated i/o cell control to connect inputs (in the high-z state) to pins. in such a case, the logic level latched into the device?s internal circuit cannot be guaranteed. (2) when the power supply on the high voltage side (hv dd ) is to be cut off by using a gated i/o cell, the same processing as described in (1) is required. this processing must be performed; otherwise, the logic level latched to the device?s internal circuit cannot be guaranteed. moreover, because special measures must be taken for cut off, please contact the sales division of epson. chapter 5 types of input/output buffers and their use (xf type) embedded array S1X60000 series epson 69 design guide 5.2.5.4 list of cells table 5-20 gated input buffers list cell name *1, *2 input level whether pull-up/pull-down resistors are included xfhiba xfhibap# xfhibad# cmos (and type) none pull-up resistor pull-up included xfhibo xfhibop# xfhibod# cmos (or type) none pull-up resistor pull-up included notes *1: the # denotes 1 or 2, with the pull-up/pull-down resistance values corresponding to type 1 and type 2, respectively (for details, refer to table 5-1). table 5-21 gated bi-directional buffers list input level function i oh /i ol cell name *1, *2 bi-directional output type 1 type 2 type 3 xfhba#t bi-directional output for high speed type 3 xfhba3at and type bi-directional output for low noise type 3 xfhba3bt bi-directional output type 1 type 2 type 3 xfhbo#t bi-directional output for high speed type 3 xfhbo3at cmos or type bi-directional output for low noise type 3 xfhbo3bt notes *1: the # denotes 1, 2, or 3, with the i oh /i ol values corresponding to type 1, type 2, and type 3, respectively (for details, refer to table 5-5). *2: in addition to the configurations shown in table 5-21, the gated bi-directional buffers may be configured with pull-up/pull-down resistors or without test pins. customers desiring to use such configurations should direct inquiries to epson. chapter 5 types of input/output buffers and their use (xf type) 70 epson embedded array S1X60000 series design guide 5.2.6 5 v tolerant fail-safe cells 5.2.6.1 overview the 5 v tolerant fail-safe cells of the S1X60000 series (xf type) allow 5.0 v interfacing without requiring a dedicated power supply. moreover, 5.0 v input signals can be received even while the hv dd power supply is cut off, allowing for greater freedom of design than ever. (however, the lv dd power supply must have voltage of 2.5 v or 2.0 v applied to it.) 5.2.6.2 features (1) there are no restrictions on the number of cells used or their placement, thus allowing customers to place the cells as required. (2) without having to install a dedicated power supply, 5.0 v signals from external sources can be interfaced. (3) no input leakage current flows even when 5.0 v signals are applied from external sources while the cell is in output mode for high level signal output. input leakage current does not occur even in input buffers that include pull-up resistors. (4) no input leakage current occurs even when 5.0 v input signals are applied while the hv dd power supply is cut off. (however, the lv dd power supply must have voltage of 2.5 v or 2.0 v applied to it.) (5) two types of cells (one for cmos level and one for cmos schmitt level) have been released. (6) because the fail-safe cells are completely cmos-structured, power consumption can be minimized. 5.2.6.3 usage precautions (1) to apply 5.0 v input signals while the hv dd power supply is cut off, always make sure the lv dd power supply has voltage of 2.5 v or 2.0 v applied to it. this is necessary due to the circuit structure of the cell. (2) about the input i/o cells ? when 5.0 v input signals are to be applied while the hv dd power supply is cut off, control pin ?c? must always be pulled low before 5.0 v input signals are applied. ? in other than cut off mode, the control signal must always be held high. if a low level input is applied to the cell terminal while the control signal remains at low levels, current may flow continuously into the input buffer. (3) about the output i/o cells ? no 5.0 v high level signals are output from the cell due to its circuit structure. therefore, if 5.0 v outputs are needed, add 5.0 v pull-up resistors external to the chip. chapter 5 types of input/output buffers and their use (xf type) embedded array S1X60000 series epson 71 design guide 5.2.6.4 list of cells table 5-22 5 v tolerant fail-safe input buffers list cell name *1 input level whether pull-up/pull-down resistors are included xfhibb xfhibbp# xfhibbd# cmos cmos cmos none pull-up resistors pull-down resistors xfhibg xfhibgp# xfhibgd# cmos schmitt cmos schmitt cmos schmitt none pull-up resistors pull-down resistors notes *1: the # denotes 1 or 2, with the pull-up resistance values corresponding to type 1 and type 2, respectively (for details, refer to table 5-1). table 5-23 rated i oh and i ol values at each voltage type of output current i oh *1 /i ol *2 (hvdd = 3.3 v) unit type 1 -3/3 ma type 2 -6/6 ma type 3 -12/12 ma notes *1: v oh = hv dd - 1.0 v *2: v ol = 0.4 v table 5-24 5 v tolerant fail-safe output buffers list function i oh /i ol cell name *1, *2 normal output type 1 type 2 xfhobf#t normal output for high speed type 3 xfhobf3at normal output for low noise type 3 xfhobf3bt 3-state output type 1 type 2 xfhtbf#t 3-state output for high speed type 3 xfhtbf3at 3-state output for low noise type 3 xfhtbf3bt notes *1: the # denotes 1, or 2, with the i oh /i ol values corresponding to type 1, and type 2, respectively (for details, refer to table 5-23). *2: in addition to the configurations shown in table 5-24, the 5 v tolerant fail-safe output buffers may be configured without test pins. customers desiring to use such configurations should direct inquiries to epson. chapter 5 types of input/output buffers and their use (xf type) 72 epson embedded array S1X60000 series design guide table 5-25 5 v tolerant fail-safe bi-directional buffers list input level function i oh /i ol cell name *1, *2 bi-directional output type 1 type 2 xfhbb#t bi-directional output for high speed type 3 xfhbb3at cmos bi-directional output for low noise type 3 xfhbb3bt bi-directional output type 1 type 2 xfhbg#t bi-directional output for high speed type 3 xfhbg3at cmos schmitt bi-directional output for low noise type 3 xfhbg3bt notes *1: the # denotes 1, or 2, with the i oh /i ol values corresponding to type 1, and type 2, respectively (for details, refer to table 5-23). *2: in addition to the configurations shown in table 5-25, the 5 v tolerant fail-safe bi-directional buffers may be configures with pull-up/pull-down resistors or without test pins. customers desiring to use such configurations should direct inquiries to epson. chapter 5 types of input/output buffers and their use (xf type) embedded array S1X60000 series epson 73 design guide 5.3 dual power supplies guidelines the S1X60000 series (xf type) allows each input/output buffer to be interfaced with 5.0 v, 3.3 v, 2.5 v, or 2.0 v signals as desired, using a dual power supply system. the internal cell area operates using a 2.5 v or 2.0 v single power supply. 5.3.1 method of adapting to dual power supplies in the S1X60000 series (xf type), it is possible to apply input signals of voltages higher the internal operating voltage using hv dd input buffers. similarly, high voltage signals above the internal operating voltage can be output using dual power supply output buffers. 5.3.2 power supplies for dual power operation if your circuit is to be operated using two different power supplies, use two power supply cells: hv dd and lv dd . specifically, hv dd may be used for hv dd input/output buffers, and lv dd may be used for lv dd input/output buffers and internal cells. the power supply voltages must always satisfy the equation below. hv dd lv dd if hv dd < lv dd , operation of the internal circuit cannot be guaranteed. the operating conditions specified below are recommended. hv dd = 3.3 v, lv dd = 2.5 v hv dd = 3.3 v, lv dd = 2.0 v 5.3.3 turning on/off dual power supplies for chips designed to dual power supply specifications, make sure the power is turned on and off in the order specified below. when turning on: lv dd (internal) hv dd (i/o section) input signals applied when turning off: input signals off hv dd (i/o section) lv dd (internal) note 1: avoid keeping only hv dd turned on (for 1 sec or more) while lv dd is turned off, so as not to degrade the chip?s reliability. note 2: when turning hv dd back on after it was off, always be sure to initialize the circuit following power on. this is necessary to ensure the internal circuit state in the event of power supply noise or the like. chapter 5 types of input/output buffers and their use (xf type) 74 epson embedded array S1X60000 series design guide 5.3.4 interface with external devices see the tables shown below when connecting input/output buffers to external lsis. 5.3.4.1 when power is supplied to hv dd table 5-26 example of connection to 3.3 v system lsis lsis to which connected S1X60000 series whether connectable remarks 3.3 v input buffer { ? 3.3 v system output buffer 5 v tolerant fail-safe input buffer { ? 3.3 v output buffer { ? 3.3 v system input buffer 5 v tolerant fail-safe output buffer { add a 3.3 v pull-up resistor as necessary. 3.3 v bi-directional buffer { ? 3.3 v system bi-directional buffer 5 v tolerant fail-safe bi-directional buffer { add a 3.3 v pull-up resistor as necessary. table 5-27 example of connection to 5.0 v system lsis lsis to which connected S1X60000 series whether connectable remarks 3.3 v input buffer ? 5.0 v system output buffer 5 v tolerant fail-safe input buffer { ? 3.3 v output buffer however, connection to 5.0 v ttl cells is possible. 5.0 v system input buffer 5 v tolerant fail-safe output buffer { a 5.0 v external pull-up resistor is required. (not required for 5.0 v ttl cells) 3.3 v bi-directional buffer ? 5.0 v system bi-directional buffer 5 v tolerant fail-safe bi-directional buffer { a 5.0 v external pull-up resistor is required. chapter 5 types of input/output buffers and their use (xf type) embedded array S1X60000 series epson 75 design guide 5.3.4.2 when power is not supplied to hv dd (lv dd = 2.5 v or 2.0 v) note that the following description assumes a case where signals are supplied from external lsis to the buffer, even while the hv dd power supply is cut off. table 5-28 example of connection to 3.3 v system lsis lsis to which connected S1X60000 series whether connectable remarks 3.3 v input buffer { be sure to use gated cells. however, input buffers with pull-up resistors cannot be used. lv dd fail-safe input buffer { for input buffers with pull-up resistors, note that input leakage current of about 30 a will flow. 3.3 v system output buffer 5 v tolerant fail-safe input buffer { ? 3.3 v bi-directional buffer ? 3.3 v system bi-directional buffer 5 v tolerant fail-safe bi-directional buffer { add a 3.3 v pull-up resistor as necessary. table 5-29 example of connection to 5.0 v system lsis lsis to which connected S1X60000 series whether connectable remarks 3.3 v input buffer ? lv dd fail-safe input buffer ? 5.0 v system output buffer 5 v tolerant fail-safe input buffer { ? 3.3 v bi-directional buffer ? 5.0 v system bi-directional buffer 5 v tolerant fail-safe bi-directional buffer { a 5.0 v external pull-up resistor is required. chapter 6 memory blocks 76 epson embedded array S1X60000 series design guide chapter 6 memory blocks the s1x 60000 series supports memory blocks.this memory block comes in the following types classified by memory capacity and function: (1) basic cell type ram (1 port or 2 port), asynchronous type (2) basic cell type ram (1 port or 2 port), synchronous type (3) standard type 1 port ram, synchronous type (4) standard type dual port ram, synchronous type (5) high density type 1 port ram, synchronous type (6) mask rom, synchronous type 6.1 basic cell type ram (asynchronous) the S1X60000 series supports 1 port ram and 2 port ram. 6.1.1 features (1) 1 port ram ? asynchronous to clock ? fully static operation ? 1 read/write address port, 1 input data port, 1 output data port ? ram configurations supported:word depth = 16 to 512 (incremental by 16 words) bit width = 1 to 64 (incremental by 1 bit) ? maximum size: 32 k bits/module (2) 2 port ram ? asynchronous to clock ? fully static operation ? 1 read address port, 1 write address port, 1 input data port, 1 output data port ? ram configurations supported: word depth = 16 to 512 (incremental by 16 words) bit width = 1 to 64 (incremental by 1 bit) ? maximum size: 32 k bits/module chapter 6 memory blocks embedded array S1X60000 series epson 77 design guide 6.1.2 ram word/bit configuration and simulation model selection ram delay parameters change depending on the word/bit structure. simulation models have been prepared using performance characteristics indicative to the ram word/bit configuration. the 1 port ram and 2 port ram word/bit structure simulation models are shown in tables 6-1 and 6-2 respectively. for ram with word/bit structures exceeding the limitations in the tables below, use combinations of multiple rams. table 6-1 simulation model selection chart (1 port ram word/bit structure) word depth bit width 16 to 64 80 to 128 144 to 192 208 to 256 272 to 320 336 to 384 400 to 448 464 to 512 1 to 16 ram1p1 ram1p5 ram1p9 ram1p13 ram1p17 ram1p21 ram1p25 ram1p29 17 to 32 ram1p2 ram1p6 ram1p10 ram1p14 ram1p18 ram1p22 ram1p26 ram1p30 33 to 48 ram1p3 ram1p7 ram1p11 ram1p15 ram1p19 ram1p23 ram1p27 ram1p31 49 to 64 ram1p4 ram1p8 ram1p12 ram1p16 ram1p20 ram1p24 ram1p28 ram1p32 table 6-2 simulation model selection chart (2 port ram word/bit structure) word depth bit width 16 to 64 80 to 128 144 to 192 208 to 256 272 to 320 336 to 384 400 to 448 464 to 512 1 to 16 ram2p1 ram2p5 ram2p9 ram2p13 ram2p17 ram2p21 ram2p25 ram2p29 17 to 32 ram2p2 ram2p6 ram2p10 ram2p14 ram2p18 ram2p22 ram2p26 ram2p30 33 to 48 ram2p3 ram2p7 ram2p11 ram2p15 ram2p19 ram2p23 ram2p27 ram2p31 49 to 64 ram2p4 ram2p8 ram2p12 ram2p16 ram2p20 ram2p24 ram2p28 ram2p32 6.1.3 ram size the x direction size, y direction size, and number of bcs used in the ram are calculated using the formulas below. the formulas below do not include the interconnect region contained in the ram. (1) 1 port ram size in the x direction: rx = 3 word/2 + 20 size in the y direction: ry = 2 bit + 12 (16 word 256) ry = 2 bit + 13 (256 < word 512) number of bcs: rambcs = rx ry table 6-3 an example of the structure of 1 port ram and number of bcs bit width word depth 8 16 32 64 64 3,248 (116 28) 5,104 (116 44) 8,816 (116 76) 16,240 (116 140) 128 5,936 (212 28) 9,328 (212 44) 16,112 (212 76) 29,680 (212 140) 256 11,312 (404 28) 17,776 (404 44) 30,704 (404 76) 56,560 (404 140) 512 22,852 (788 29) 35,460 (788 45) 60,676 (788 77) 111,108 (788 141) chapter 6 memory blocks 78 epson embedded array S1X60000 series design guide (2) 2 port ram size in the x direction: rx = 3 word/2 + 20 size in the y direction: ry = 2 bit + 15 (16 word 256) ry = 2 bit + 17 (256 < word 512) number of bcs: rambcs = rx ry table 6-4 an example of the structure of 2 port ram and number of bcs bit width word depth 8 16 32 64 64 3,596 (116 31) 5,452 (116 47) 9,164 (116 79) 16,588 (116 143) 128 6,572 (212 31) 9,964 (212 47) 16,748 (212 79) 30,316 (212 143) 256 12,524 (404 31) 18,988 (404 47) 31,916 (404 79) 57,772 (404 143) 512 26,004 (788 33) 38,612 (788 49) 63,828 (788 81) 114,260 (788 145) chapter 6 memory blocks embedded array S1X60000 series epson 79 design guide 6.1.4 investigating ram placement on master slice when investigating ram placement on a master slice, please insure that sufficient area is available in both the x direction (column) and the y direction (row). when loading ram onto a chip, it is necessary to insure that the capacity of the master exceeds the required ram area in both the x and y directions. when multiple rams are used, ram blocks are placed adjacent to each other either horizontally or vertically. the wiring areas around ram are not included in the equation shown in the previous section. it is therefore not possible to determine the advantages and disadvantages of placing ram on the master slice based on values obtained by simply adding rxsize and rysize to the sizes in the x and y directions, respectively. as shown in figure 6-1, add the interconnecting area of bit/2 bc (round up to the nearest whole number) to x direction and every 1 bc to the upper and lower of y direction, then the regarding master slice selection should be decided to mount or not. 256w 16b ram 4 412 ram (1) ram (1) ram (1) ram (1) 184 404 44 46 46 46 46 46 1 8 1 figure 6-1 example of ram layout chapter 6 memory blocks 80 epson embedded array S1X60000 series design guide 6.1.5 explanation of functions (1) 1 port ram table 6-5-1 1 port ram signals signal name i/o function cs in chip select signal, h: ram active rw in read/write signal, h: read, l: write a0, a1, ..., a (m-1) in read/write address port, a0: lsb d0, d1, ..., d (n-1) in data input port, d0: lsb y0, y1, ..., y (n-1) out data output port, y0: lsb table 6-5-2 fi, fo of 1 port ram fi fo a0 a1 a2 a3 a4 a5 a6 a7 a8 cs rw d* y* 16 to 64 1lu 1lu 1lu 1lu 1lu 1lu 1lu 1lu 2lu 28.9lu 80 to 128 1lu 1lu 1lu 1lu 1lu 1lu 1lu 1lu 1lu 2lu 28.9lu 144 to 256 1lu 2lu 2lu 2lu 1lu 1lu 1lu 1lu 1lu 1lu 2lu 28.9lu 272 to 512 1lu 2lu 2lu 2lu 2lu 2lu 2lu 1lu 1lu 1lu 1lu 2lu 28.9lu k of y * corresponds ?in4? table 6-6 1 port ram truth table cs rw a0, a1 ... a (m-1) y0, y1 ... y (n-1) mode 0 x x unknown wait 1 0 stable unknown write 1 1 stable read data read x: high or low ? data read data read data read data read the data is read by holding cs at high and rw at high and setting the address. ? data write data write data write data write the data can be written in either of the following two ways: (1) holding cs at high, setting the address, and sending a negative pulse to rw. (2) holding rw at low, setting the address, and sending a positive pulse to cs. when either method is used, the data is latched to the ram at the trailing edge of the pulse. chapter 6 memory blocks embedded array S1X60000 series epson 81 design guide ? the wait state the wait state the wait state the wait state when cs is low, the 1 port ram enters a wait state and only maintains the data. the current consumed by the ram is merely the leakage current, and is almost zero. (2) 2 port ram table 6-7-1 2 port ram signals signal name i/o function cs in chip select signal, h: ram active rd in read signal, h: read enable wr in write signal, h: write enable ra0, ... ra (m-1) in read address port, ra0: lsb wa0, ... wa (m-1) in write address port, wa0: lsb d0, d1, ... d (n-1) in data input port, d0: lsb y0, y1, ... y (n-1) out data output port, y0: lsb table 6-7-2 fi, fo of 2 port ram fi fo ra0/ wa0 ra1/ wa1 ra2/ wa2 ra3/ wa3 ra4/ wa4 ra5/ wa5 ra6/ wa6 ra7/ wa7 ra8/ wa8 cs rd wr d* y* 64 1lu 1lu 1lu 1lu 1lu 1lu 1lu 1lu 1lu 2lu 28.9lu 128 1lu 1lu 1lu 1lu 1lu 1lu 1lu 1lu 1lu 1lu 2lu 28.9lu 256 1lu 2lu 2lu 2lu 1lu 1lu 1lu 1lu 1lu 1lu 1lu 2lu 28.9lu 512 1lu 2lu 2lu 2lu 2lu 2.1lu 2lu 1lu 1lu 1lu 1lu 1lu 2lu 28.9lu k of y * corresponds ?in4? table 6-8 2 port ram truth table cs rd wr ra0, ... ra (n-1) wa0, ..., wa (m-1) y0, ... y (n-1) mode 0 x x x x unknown wait 1 0 0 x x unknown wait 1 0 1 x stable unknown write 1 1 0 stable x read data read 1 1 1 stable stable read data read & write x: high or low chapter 6 memory blocks 82 epson embedded array S1X60000 series design guide ? data read data read data read data read the data is read by holding cs at high and rd at high and setting the read address. ? data write data write data write data write the data can be written in either of the following two ways: (1) holding cs at high, setting the write address, and sending a positive pulse to wr. (2) holding wr at high, setting the write address, and sending a positive pulse to cs. ? data read/write data read/write data read/write data read/write when reading is done at the same time as writing, it is possible by performing the respective methods simultaneously. however, these two operations cannot be performed simultaneously on the same address. the read cycle access time described at section 6.1.6 applies to data for which the writing has already been completed. ? the wait state the wait state the wait state the wait state the 2 port ram enters a wait state in either of the situations below, and does nothing but maintain its data. the current consumed by the ram is merely the leakage current, and is almost 0. (1) cs is low. (2) cs is high, rd is low, and wr is low. chapter 6 memory blocks embedded array S1X60000 series epson 83 design guide 6.1.6 delay parameters (1) 2.5 v specifications (v dd = 2.3 to 2.7 v, t a = -40 to +85c) table 6-9 1 port/2 port ram read cycle (1/8) ram1p1/ ram2p1 ram1p2/ ram2p2 ram1p3/ ram2p3 ram1p4/ ram2p4 parameter signal min. max. min. max. min. max. min. max. unit read cycle t rc 4.605 ? 5.239 ? 5.519 ? 6.203 ? address access time t acc ? 4.605 ? 5.239 ? 5.519 ? 6.203 cs access time t acs ? 4.605 ? 5.239 ? 5.519 ? 6.203 rw access time t arw ? 4.605 ? 5.239 ? 5.519 ? 6.203 cs active time t rcs 4.605 ? 5.239 ? 5.519 ? 6.203 ? output hold time after address change t oh 0.093 ? 0.153 ? 0.212 ? 0.272 ? output hold time after cs disable t ohcs 0.093 ? 0.153 ? 0.212 ? 0.272 ? output hold time after rw disable t ohrw 0.093 ? 0.153 ? 0.212 ? 0.272 ? ns table 6-9 1 port/2 port ram read cycle (2/8) ram1p5/ ram2p5 ram1p6/ ram2p6 ram1p7/ ram2p7 ram1p8/ ram2p8 parameter signal min. max. min. max. min. max. min. max. unit read cycle t rc 5.668 ? 6.302 ? 6.581 ? 7.266 ? address access time t acc ? 5.668 ? 6.302 ? 6.581 ? 7.266 cs access time t acs ? 5.668 ? 6.302 ? 6.581 ? 7.266 rw access time t arw ? 5.668 ? 6.302 ? 6.581 ? 7.266 cs active time t rcs 5.668 ? 6.302 ? 6.581 ? 7.266 ? output hold time after address change t oh 0.093 ? 0.153 ? 0.212 ? 0.272 ? output hold time after cs disable t ohcs 0.093 ? 0.153 ? 0.212 ? 0.272 ? output hold time after rw disable t ohrw 0.093 ? 0.153 ? 0.212 ? 0.272 ? ns chapter 6 memory blocks 84 epson embedded array S1X60000 series design guide (1) 2.5 v specifications (v dd = 2.3 to 2.7 v, t a = -40 to +85c) table 6-9 1 port/2 port ram read cycle (3/8) ram1p9/ ram2p9 ram1p10/ ram2p10 ram1p11/ ram2p11 ram1p12/ ram2p12 parameter signal min. max. min. max. min. max. min. max. unit read cycle t rc 6.731 ? 7.365 ? 7.644 ? 8.328 ? address access time t acc ? 6.731 ? 7.365 ? 7.644 ? 8.328 cs access time t acs ? 6.731 ? 7.365 ? 7.644 ? 8.328 rw access time t arw ? 6.731 ? 7.365 ? 7.644 ? 8.328 cs active time t rcs 6.731 ? 7.365 ? 7.644 ? 8.328 ? output hold time after address change t oh 0.093 ? 0.153 ? 0.212 ? 0.272 ? output hold time after cs disable t ohcs 0.093 ? 0.153 ? 0.212 ? 0.272 ? output hold time after rw disable t ohrw 0.093 ? 0.153 ? 0.212 ? 0.272 ? ns table 6-9 1 port/2 port ram read cycle (4/8) ram1p13/ ram2p13 ram1p14/ ram2p14 ram1p15/ ram2p15 ram1p16/ ram2p16 parameter signal min. max. min. max. min. max. min. max. unit read cycle t rc 7.794 ? 8.428 ? 8.707 ? 9.391 ? address access time t acc ? 7.794 ? 8.428 ? 8.707 ? 9.391 cs access time t acs ? 7.794 ? 8.428 ? 8.707 ? 9.391 rw access time t arw ? 7.794 ? 8.428 ? 8.707 ? 9.391 cs active time t rcs 7.794 ? 8.428 ? 8.707 ? 9.391 ? output hold time after address change t oh 0.093 ? 0.153 ? 0.212 ? 0.272 ? output hold time after cs disable t ohcs 0.093 ? 0.153 ? 0.212 ? 0.272 ? output hold time after rw disable t ohrw 0.093 ? 0.153 ? 0.212 ? 0.272 ? ns chapter 6 memory blocks embedded array S1X60000 series epson 85 design guide (1) 2.5 v specifications (v dd = 2.3 to 2.7 v, t a = -40 to +85c) table 6-9 1 port/2 port ram read cycle (5/8) ram1p17/ ram2p17 ram1p18/ ram2p18 ram1p19/ ram2p19 ram1p20/ ram2p20 parameter signal min. max. min. max. min. max. min. max. unit read cycle t rc 8.856 ? 9.490 ? 9.770 ? 10.454 ? address access time t acc ? 8.856 ? 9.490 ? 9.770 ? 10.454 cs access time t acs ? 8.856 ? 9.490 ? 9.770 ? 10.454 rw access time t arw ? 8.856 ? 9.490 ? 9.770 ? 10.454 cs active time t rcs 8.856 ? 9.490 ? 9.770 ? 10.454 ? output hold time after address change t oh 0.093 ? 0.153 ? 0.212 ? 0.272 ? output hold time after cs disable t ohcs 0.093 ? 0.153 ? 0.212 ? 0.272 ? output hold time after rw disable t ohrw 0.093 ? 0.153 ? 0.212 ? 0.272 ? ns table 6-9 1 port/2 port ram read cycle (6/8) ram1p21/ ram2p21 ram1p22/ ram2p22 ram1p23/ ram2p23 ram1p24/ ram2p24 parameter signal min. max. min. max. min. max. min. max. unit read cycle t rc 9.919 ? 10.553 ? 10.832 ? 11.517 ? address access time t acc ? 9.919 ? 10.553 ? 10.832 ? 11.517 cs access time t acs ? 9.919 ? 10.553 ? 10.832 ? 11.517 rw access time t arw ? 9.919 ? 10.553 ? 10.832 ? 11.517 cs active time t rcs 9.919 ? 10.553 ? 10.832 ? 11.517 ? output hold time after address change t oh 0.093 ? 0.153 ? 0.212 ? 0.272 ? output hold time after cs disable t ohcs 0.093 ? 0.153 ? 0.212 ? 0.272 ? output hold time after rw disable t ohrw 0.093 ? 0.153 ? 0.212 ? 0.272 ? ns chapter 6 memory blocks 86 epson embedded array S1X60000 series design guide (1) 2.5 v specifications (v dd = 2.3 to 2.7 v, t a = -40 to +85c) table 6-9 1 port/2 port ram read cycle (7/8) ram1p25/ ram2p25 ram1p26/ ram2p26 ram1p27/ ram2p27 ram1p28/ ram2p28 parameter signal min. max. min. max. min. max. min. max. unit read cycle t rc 10.982 ? 11.616 ? 11.895 ? 12.579 ? address access time t acc ? 10.982 ? 11.616 ? 11.895 ? 12.579 cs access time t acs ? 10.982 ? 11.616 ? 11.895 ? 12.579 rw access time t arw ? 10.982 ? 11.616 ? 11.895 ? 12.579 cs active time t rcs 10.982 ? 11.616 ? 11.895 ? 12.579 ? output hold time after address change t oh 0.093 ? 0.153 ? 0.212 ? 0.272 ? output hold time after cs disable t ohcs 0.093 ? 0.153 ? 0.212 ? 0.272 ? output hold time after rw disable t ohrw 0.093 ? 0.153 ? 0.212 ? 0.272 ? ns table 6-9 1 port/2 port ram read cycle (8/8) ram1p29/ ram2p29 ram1p30/ ram2p30 ram1p31/ ram2p31 ram1p32/ ram2p32 parameter signal min. max. min. max. min. max. min. max. unit read cycle t rc 12.045 ? 12.679 ? 12.958 ? 13.642 ? address access time t acc ? 12.045 ? 12.679 ? 12.958 ? 13.642 cs access time t acs ? 12.045 ? 12.679 ? 12.958 ? 13.642 rw access time t arw ? 12.045 ? 12.679 ? 12.958 ? 13.642 cs active time t rcs 12.045 ? 12.679 ? 12.958 ? 13.642 ? output hold time after address change t oh 0.093 ? 0.153 ? 0.212 ? 0.272 ? output hold time after cs disable t ohcs 0.093 ? 0.153 ? 0.212 ? 0.272 ? output hold time after rw disable t ohrw 0.093 ? 0.153 ? 0.212 ? 0.272 ? ns chapter 6 memory blocks embedded array S1X60000 series epson 87 design guide (1) 2.5 v specifications (v dd = 2.3 to 2.7 v, t a = -40 to +85c) table 6-10 1 port/2 port ram write cycle (1/8) ram1p1/ ram2p1 ram1p2/ ram2p2 ram1p3/ ram2p3 ram1p4/ ram2p4 parameter signal min. max. min. max. min. max. min. max. unit write cycle t wc 2.776 ? 3.624 ? 4.520 ? 5.396 ? write pulse width t wp 1.347 ? 2.223 ? 3.101 ? 3.977 ? cs active time t wcs 1.347 ? 2.223 ? 3.101 ? 3.977 ? address setup time t as 0.481 ? 0.481 ? 0.481 ? 0.481 ? address hold time t v 0.938 ? 0.938 ? 0.938 ? 0.938 ? data setup time t ds 0.000 ? 0.000 ? 0.000 ? 0.000 ? data hold time t dh 1.671 ? 2.374 ? 3.078 ? 3.781 ? ns table 6-10 1 port/2 port ram write cycle (2/8) ram1p5/ ram2p5 ram1p6/ ram2p6 ram1p7/ ram2p7 ram1p8/ ram2p8 parameter signal min. max. min. max. min. max. min. max. unit write cycle t wc 2.924 ? 3.799 ? 4.677 ? 5.553 ? write pulse width t wp 1.425 ? 2.300 ? 3.178 ? 4.054 ? cs active time t wcs 1.425 ? 2.300 ? 3.178 ? 4.054 ? address setup time t as 0.561 ? 0.561 ? 0.561 ? 0.561 ? address hold time t v 0.938 ? 0.938 ? 0.938 ? 0.938 ? data setup time t ds 0.000 ? 0.000 ? 0.000 ? 0.000 ? data hold time t dh 1.731 ? 2.434 ? 3.138 ? 3.841 ? ns chapter 6 memory blocks 88 epson embedded array S1X60000 series design guide (1) 2.5 v specifications (v dd = 2.3 to 2.7 v, t a = -40 to +85c) table 6-10 1 port/2 port ram write cycle (3/8) ram1p9/ ram2p9 ram1p10/ ram2p10 ram1p11/ ram2p11 ram1p12/ ram2p12 parameter signal min. max. min. max. min. max. min. max. unit write cycle t wc 3.092 ? 3.968 ? 4.846 ? 5.722 ? write pulse width t wp 1.513 ? 2.389 ? 3.267 ? 4.143 ? cs active time t wcs 1.513 ? 2.389 ? 3.267 ? 4.143 ? address setup time t as 0.641 ? 0.641 ? 0.641 ? 0.641 ? address hold time t v 0.938 ? 0.938 ? 0.938 ? 0.938 ? data setup time t ds 0.000 ? 0.000 ? 0.000 ? 0.000 ? data hold time t dh 1.791 ? 2.495 ? 3.198 ? 3.901 ? ns table 6-10 1 port/2 port ram write cycle (4/8) ram1p13/ ram2p13 ram1p14/ ram2p14 ram1p15/ ram2p15 ram1p16/ ram2p16 parameter signal min. max. min. max. min. max. min. max. unit write cycle t wc 3.273 ? 4.148 ? 5.026 ? 5.902 ? write pulse width t wp 1.614 ? 2.489 ? 3.367 ? 4.243 ? cs active time t wcs 1.614 ? 2.489 ? 3.367 ? 4.243 ? address setup time t as 0.721 ? 0.721 ? 0.721 ? 0.721 ? address hold time t v 0.938 ? 0.938 ? 0.938 ? 0.938 ? data setup time t ds 0.000 ? 0.000 ? 0.000 ? 0.000 ? data hold time t dh 1.851 ? 2.555 ? 3.258 ? 3.961 ? ns chapter 6 memory blocks embedded array S1X60000 series epson 89 design guide (1) 2.5 v specifications (v dd = 2.3 to 2.7 v, t a = -40 to +85c) table 6-10 1 port/2 port ram write cycle (5/8) ram1p17/ ram2p17 ram1p18/ ram2p18 ram1p19/ ram2p19 ram1p20/ ram2p20 parameter signal min. max. min. max. min. max. min. max. unit write cycle t wc 3.397 ? 4.272 ? 5.150 ? 6.026 ? write pulse width t wp 1.679 ? 2.554 ? 3.432 ? 4.308 ? cs active time t wcs 1.679 ? 2.554 ? 3.432 ? 4.308 ? address setup time t as 0.780 ? 0.780 ? 0.780 ? 0.780 ? address hold time t v 0.938 ? 0.938 ? 0.938 ? 0.938 ? data setup time t ds 0.000 ? 0.000 ? 0.000 ? 0.000 ? data hold time t dh 1.895 ? 2.593 ? 3.296 ? 4.000 ? ns table 6-10 1 port/2 port ram write cycle (6/8) ram1p21/ ram2p21 ram1p22/ ram2p22 ram1p23/ ram2p23 ram1p24/ ram2p24 parameter signal min. max. min. max. min. max. min. max. unit write cycle t wc 3.558 ? 4.443 ? 5.311 ? 6.188 ? write pulse width t wp 1.764 ? 2.639 ? 3.517 ? 4.394 ? cs active time t wcs 1.764 ? 2.639 ? 3.517 ? 4.394 ? address setup time t as 0.856 ? 0.856 ? 0.856 ? 0.856 ? address hold time t v 0.938 ? 0.938 ? 0.938 ? 0.938 ? data setup time t ds 0.000 ? 0.000 ? 0.000 ? 0.000 ? data hold time t dh 1.952 ? 2.650 ? 3.353 ? 4.057 ? ns chapter 6 memory blocks 90 epson embedded array S1X60000 series design guide (1) 2.5 v specifications (v dd = 2.3 to 2.7 v, t a = -40 to +85c) table 6-10 1 port/2 port ram write cycle (7/8) ram1p25/ ram2p25 ram1p26/ ram2p26 ram1p27/ ram2p27 ram1p28/ ram2p28 parameter signal min. max. min. max. min. max. min. max. unit write cycle t wc 3.720 ? 4.595 ? 5.473 ? 6.349 ? write pulse width t wp 1.850 ? 2.725 ? 3.603 ? 4.479 ? cs active time t wcs 1.850 ? 2.725 ? 3.603 ? 4.479 ? address setup time t as 0.932 ? 0.932 ? 0.932 ? 0.932 ? address hold time t v 0.938 ? 0.938 ? 0.938 ? 0.938 ? data setup time t ds 0.000 ? 0.000 ? 0.000 ? 0.000 ? data hold time t dh 2.009 ? 2.707 ? 3.410 ? 4.113 ? ns table 6-10 1 port/2 port ram write cycle (8/8) ram1p29/ ram2p29 ram1p30/ ram2p30 ram1p31/ ram2p31 ram1p32/ ram2p32 parameter signal min. max. min. max. min. max. min. max. unit write cycle t wc 3.880 ? 4.755 ? 5.633 ? 6.509 ? write pulse width t wp 1.935 ? 2.810 ? 3.688 ? 4.564 ? cs active time t wcs 1.935 ? 2.810 ? 3.688 ? 4.564 ? address setup time t as 1.007 ? 1.007 ? 1.007 ? 1.007 ? address hold time t v 0.938 ? 0.938 ? 0.938 ? 0.938 ? data setup time t ds 0.000 ? 0.000 ? 0.000 ? 0.000 ? data hold time t dh 2.066 ? 2.764 ? 3.467 ? 4.170 ? ns chapter 6 memory blocks embedded array S1X60000 series epson 91 design guide (2) 2.5 v specifications (v dd = 2.3 to 2.7 v, t a = 0 to +70c) table 6-11 1 port/2 port ram read cycle (1/8) ram1p1/ ram2p1 ram1p2/ ram2p2 ram1p3/ ram2p3 ram1p4/ ram2p4 parameter signal min. max. min. max. min. max. min. max. unit read cycle t rc 4.356 ? 4.956 ? 5.220 ? 5.868 ? address access time t acc ? 4.356 ? 4.956 ? 5.220 ? 5.868 cs access time t acs ? 4.356 ? 4.956 ? 5.220 ? 5.868 rw access time t arw ? 4.356 ? 4.956 ? 5.220 ? 5.868 cs active time t rcs 4.356 ? 4.956 ? 5.220 ? 5.868 ? output hold time after address change t oh 0.099 ? 0.163 ? 0.226 ? 0.289 ? output hold time after cs disable t ohcs 0.099 ? 0.163 ? 0.226 ? 0.289 ? output hold time after rw disable t ohrw 0.099 ? 0.163 ? 0.226 ? 0.289 ? ns table 6-11 1 port/2 port ram read cycle (2/8) ram1p5/ ram2p5 ram1p6/ ram2p6 ram1p7/ ram2p7 ram1p8/ ram2p8 parameter signal min. max. min. max. min. max. min. max. unit read cycle t rc 5.362 ? 5.961 ? 6.226 ? 6.873 ? address access time t acc ? 5.362 ? 5.961 ? 6.226 ? 6.873 cs access time t acs ? 5.362 ? 5.961 ? 6.226 ? 6.873 rw access time t arw ? 5.362 ? 5.961 ? 6.226 ? 6.873 cs active time t rcs 5.362 ? 5.961 ? 6.226 ? 6.873 ? output hold time after address change t oh 0.099 ? 0.163 ? 0.226 ? 0.289 ? output hold time after cs disable t ohcs 0.099 ? 0.163 ? 0.226 ? 0.289 ? output hold time after rw disable t ohrw 0.099 ? 0.163 ? 0.226 ? 0.289 ? ns chapter 6 memory blocks 92 epson embedded array S1X60000 series design guide (2) 2.5 v specifications (v dd = 2.3 to 2.7 v, t a = 0 to +70c) table 6-11 1 port/2 port ram read cycle (3/8) ram1p9/ ram2p9 ram1p10/ ram2p10 ram1p11/ ram2p11 ram1p12/ ram2p12 parameter signal min. max. min. max. min. max. min. max. unit read cycle t rc 6.367 ? 6.967 ? 7.231 ? 7.878 ? address access time t acc ? 6.367 ? 6.967 ? 7.231 ? 7.878 cs access time t acs ? 6.367 ? 6.967 ? 7.231 ? 7.878 rw access time t arw ? 6.367 ? 6.967 ? 7.231 ? 7.878 cs active time t rcs 6.367 ? 6.967 ? 7.231 ? 7.878 ? output hold time after address change t oh 0.099 ? 0.163 ? 0.226 ? 0.289 ? output hold time after cs disable t ohcs 0.099 ? 0.163 ? 0.226 ? 0.289 ? output hold time after rw disable t ohrw 0.099 ? 0.163 ? 0.226 ? 0.289 ? ns table 6-11 1 port/2 port ram read cycle (4/8) ram1p13/ ram2p13 ram1p14/ ram2p14 ram1p15/ ram2p15 ram1p16/ ram2p16 parameter signal min. max. min. max. min. max. min. max. unit read cycle t rc 7.372 ? 7.972 ? 8.236 ? 8.884 ? address access time t acc ? 7.372 ? 7.972 ? 8.236 ? 8.884 cs access time t acs ? 7.372 ? 7.972 ? 8.236 ? 8.884 rw access time t arw ? 7.372 ? 7.972 ? 8.236 ? 8.884 cs active time t rcs 7.372 ? 7.972 ? 8.236 ? 8.884 ? output hold time after address change t oh 0.099 ? 0.163 ? 0.226 ? 0.289 ? output hold time after cs disable t ohcs 0.099 ? 0.163 ? 0.226 ? 0.289 ? output hold time after rw disable t ohrw 0.099 ? 0.163 ? 0.226 ? 0.289 ? ns chapter 6 memory blocks embedded array S1X60000 series epson 93 design guide (2) 2.5 v specifications (v dd = 2.3 to 2.7 v, t a = 0 to +70c) table 6-11 1 port/2 port ram read cycle (5/8) ram1p17/ ram2p17 ram1p18/ ram2p18 ram1p19/ ram2p19 ram1p20/ ram2p20 parameter signal min. max. min. max. min. max. min. max. unit read cycle t rc 8.378 ? 8.977 ? 9.242 ? 9.889 ? address access time t acc ? 8.378 ? 8.977 ? 9.242 ? 9.889 cs access time t acs ? 8.378 ? 8.977 ? 9.242 ? 9.889 rw access time t arw ? 8.378 ? 8.977 ? 9.242 ? 9.889 cs active time t rcs 8.378 ? 8.977 ? 9.242 ? 9.889 ? output hold time after address change t oh 0.099 ? 0.163 ? 0.226 ? 0.289 ? output hold time after cs disable t ohcs 0.099 ? 0.163 ? 0.226 ? 0.289 ? output hold time after rw disable t ohrw 0.099 ? 0.163 ? 0.226 ? 0.289 ? ns table 6-11 1 port/2 port ram read cycle (6/8) ram1p21/ ram2p21 ram1p22/ ram2p22 ram1p23/ ram2p23 ram1p24/ ram2p24 parameter signal min. max. min. max. min. max. min. max. unit read cycle t rc 9.383 ? 9.983 ? 10.247 ? 10.894 ? address access time t acc ? 9.383 ? 9.983 ? 10.247 ? 10.894 cs access time t acs ? 9.383 ? 9.983 ? 10.247 ? 10.894 rw access time t arw ? 9.383 ? 9.983 ? 10.247 ? 10.894 cs active time t rcs 9.383 ? 9.983 ? 10.247 ? 10.894 ? output hold time after address change t oh 0.099 ? 0.163 ? 0.226 ? 0.289 ? output hold time after cs disable t ohcs 0.099 ? 0.163 ? 0.226 ? 0.289 ? output hold time after rw disable t ohrw 0.099 ? 0.163 ? 0.226 ? 0.289 ? ns chapter 6 memory blocks 94 epson embedded array S1X60000 series design guide (2) 2.5 v specifications (v dd = 2.3 to 2.7 v, t a = 0 to +70c) table 6-11 1 port/2 port ram read cycle (7/8) ram1p25/ ram2p25 ram1p26/ ram2p26 ram1p27/ ram2p27 ram1p28/ ram2p28 parameter signal min. max. min. max. min. max. min. max. unit read cycle t rc 10.388 ? 10.988 ? 11.252 ? 11.900 ? address access time t acc ? 10.388 ? 10.988 ? 11.252 ? 11.900 cs access time t acs ? 10.388 ? 10.988 ? 11.252 ? 11.900 rw access time t arw ? 10.388 ? 10.988 ? 11.252 ? 11.900 cs active time t rcs 10.388 ? 10.988 ? 11.252 ? 11.900 ? output hold time after address change t oh 0.099 ? 0.163 ? 0.226 ? 0.289 ? output hold time after cs disable t ohcs 0.099 ? 0.163 ? 0.226 ? 0.289 ? output hold time after rw disable t ohrw 0.099 ? 0.163 ? 0.226 ? 0.289 ? ns table 6-11 1 port/2 port ram read cycle (8/8) ram1p29/ ram2p29 ram1p30/ ram2p30 ram1p31/ ram2p31 ram1p32/ ram2p32 parameter signal min. max. min. max. min. max. min. max. unit read cycle t rc 11.394 ? 11.993 ? 12.257 ? 12.905 ? address access time t acc ? 11.394 ? 11.993 ? 12.257 ? 12.905 cs access time t acs ? 11.394 ? 11.993 ? 12.257 ? 12.905 rw access time t arw ? 11.394 ? 11.993 ? 12.257 ? 12.905 cs active time t rcs 11.394 ? 11.993 ? 12.257 ? 12.905 ? output hold time after address change t oh 0.099 ? 0.163 ? 0.226 ? 0.289 ? output hold time after cs disable t ohcs 0.099 ? 0.163 ? 0.226 ? 0.289 ? output hold time after rw disable t ohrw 0.099 ? 0.163 ? 0.226 ? 0.289 ? ns chapter 6 memory blocks embedded array S1X60000 series epson 95 design guide (2) 2.5 v specifications (v dd = 2.3 to 2.7 v, t a = 0 to +70c) table 6-12 1 port/2 port ram write cycle (1/8) ram1p1/ ram2p1 ram1p2/ ram2p2 ram1p3/ ram2p3 ram1p4/ ram2p4 parameter signal min. max. min. max. min. max. min. max. unit write cycle t wc 2.617 ? 3.444 ? 4.275 ? 5.104 ? write pulse width t wp 1.275 ? 2.102 ? 2.933 ? 3.762 ? cs active time t wcs 1.275 ? 2.102 ? 2.933 ? 3.762 ? address setup time t as 0.455 ? 0.455 ? 0.455 ? 0.455 ? address hold time t ah 0.887 ? 0.887 ? 0.887 ? 0.887 ? data setup time t ds 0.000 ? 0.000 ? 0.000 ? 0.000 ? data hold time t dh 1.581 ? 2.246 ? 2.911 ? 3.577 ? ns table 6-12 1 port/2 port ram write cycle (2/8) ram1p5/ ram2p5 ram1p6/ ram2p6 ram1p7/ ram2p7 ram1p8/ ram2p8 parameter signal min. max. min. max. min. max. min. max. unit write cycle t wc 2.766 ? 3.594 ? 4.424 ? 5.253 ? write pulse width t wp 1.348 ? 2.176 ? 3.006 ? 3.835 ? cs active time t wcs 1.348 ? 2.176 ? 3.006 ? 3.835 ? address setup time t as 0.531 ? 0.531 ? 0.531 ? 0.531 ? address hold time t ah 0.887 ? 0.887 ? 0.887 ? 0.887 ? data setup time t ds 0.000 ? 0.000 ? 0.000 ? 0.000 ? data hold time t dh 1.638 ? 2.303 ? 2.968 ? 3.633 ? ns chapter 6 memory blocks 96 epson embedded array S1X60000 series design guide (2) 2.5 v specifications (v dd = 2.3 to 2.7 v, t a = 0 to +70c) table 6-12 1 port/2 port ram write cycle (3/8) ram1p9/ ram2p9 ram1p10/ ram2p10 ram1p11/ ram2p11 ram1p12/ ram2p12 parameter signal min. max. min. max. min. max. min. max. unit write cycle t wc 2.926 ? 3.754 ? 4.584 ? 5.413 ? write pulse width t wp 1.432 ? 2.260 ? 3.090 ? 3.919 ? cs active time t wcs 1.432 ? 2.260 ? 3.090 ? 3.919 ? address setup time t as 0.607 ? 0.607 ? 0.607 ? 0.607 ? address hold time t ah 0.887 ? 0.887 ? 0.887 ? 0.887 ? data setup time t ds 0.000 ? 0.000 ? 0.000 ? 0.000 ? data hold time t dh 1.694 ? 2.360 ? 3.025 ? 3.690 ? ns table 6-12 1 port/2 port ram write cycle (4/8) ram1p13/ ram2p13 ram1p14/ ram2p14 ram1p15/ ram2p15 ram1p16/ ram2p16 parameter signal min. max. min. max. min. max. min. max. unit write cycle t wc 3.096 ? 3.923 ? 4.754 ? 5.583 ? write pulse width t wp 1.527 ? 2.354 ? 3.185 ? 4.014 ? cs active time t wcs 1.527 ? 2.354 ? 3.185 ? 4.014 ? address setup time t as 0.682 ? 0.682 ? 0.682 ? 0.682 ? address hold time t ah 0.887 ? 0.887 ? 0.887 ? 0.887 ? data setup time t ds 0.000 ? 0.000 ? 0.000 ? 0.000 ? data hold time t dh 1.751 ? 2.416 ? 3.082 ? 3.747 ? ns chapter 6 memory blocks embedded array S1X60000 series epson 97 design guide (2) 2.5 v specifications (v dd = 2.3 to 2.7 v, t a = 0 to +70c) table 6-12 1 port/2 port ram write cycle (5/8) ram1p17/ ram2p17 ram1p18/ ram2p18 ram1p19/ ram2p19 ram1p20/ ram2p20 parameter signal min. max. min. max. min. max. min. max. unit write cycle t wc 3.213 ? 4.041 ? 4.872 ? 5.701 ? write pulse width t wp 1.588 ? 2.416 ? 3.247 ? 4.076 ? cs active time t wcs 1.588 ? 2.416 ? 3.247 ? 4.076 ? address setup time t as 0.738 ? 0.738 ? 0.738 ? 0.738 ? address hold time t ah 0.887 ? 0.887 ? 0.887 ? 0.887 ? data setup time t ds 0.000 ? 0.000 ? 0.000 ? 0.000 ? data hold time t dh 1.793 ? 2.453 ? 3.118 ? 3.784 ? ns table 6-12 1 port/2 port ram write cycle (6/8) ram1p21/ ram2p21 ram1p22/ ram2p22 ram1p23/ ram2p23 ram1p24/ ram2p24 parameter signal min. max. min. max. min. max. min. max. unit write cycle t wc 3.366 ? 4.194 ? 5.024 ? 5.853 ? write pulse width t wp 1.669 ? 2.497 ? 3.327 ? 4.156 ? cs active time t wcs 1.669 ? 2.497 ? 3.327 ? 4.156 ? address setup time t as 0.810 ? 0.810 ? 0.810 ? 0.810 ? address hold time t ah 0.887 ? 0.887 ? 0.887 ? 0.887 ? data setup time t ds 0.000 ? 0.000 ? 0.000 ? 0.000 ? data hold time t dh 1.847 ? 2.507 ? 3.172 ? 3.837 ? ns chapter 6 memory blocks 98 epson embedded array S1X60000 series design guide (2) 2.5 v specifications (v dd = 2.3 to 2.7 v, t a = 0 to +70c) table 6-12 1 port/2 port ram write cycle (7/8) ram1p25/ ram2p25 ram1p26/ ram2p26 ram1p27/ ram2p27 ram1p28/ ram2p28 parameter signal min. max. min. max. min. max. min. max. unit write cycle t wc 3.518 ? 4.345 ? 5.176 ? 6.005 ? write pulse width t wp 1.750 ? 2.577 ? 3.408 ? 4.237 ? cs active time t wcs 1.750 ? 2.577 ? 3.408 ? 4.237 ? address setup time t as 0.881 ? 0.881 ? 0.881 ? 0.881 ? address hold time t ah 0.887 ? 0.887 ? 0.887 ? 0.887 ? data setup time t ds 0.000 ? 0.000 ? 0.000 ? 0.000 ? data hold time t dh 1.900 ? 2.560 ? 3.226 ? 3.891 ? ns table 6-12 1 port/2 port ram write cycle (8/8) ram1p29/ ram2p29 ram1p30/ ram2p30 ram1p31/ ram2p31 ram1p32/ ram2p32 parameter signal min. max. min. max. min. max. min. max. unit write cycle t wc 3.670 ? 4.498 ? 5.329 ? 6.157 ? write pulse width t wp 1.830 ? 2.658 ? 3.489 ? 4.317 ? cs active time t wcs 1.830 ? 2.658 ? 3.489 ? 4.317 ? address setup time t as 0.953 ? 0.953 ? 0.953 ? 0.953 ? address hold time t ah 0.887 ? 0.887 ? 0.887 ? 0.887 ? data setup time t ds 0.000 ? 0.000 ? 0.000 ? 0.000 ? data hold time t dh 1.954 ? 2.614 ? 3.280 ? 3.945 ? ns chapter 6 memory blocks embedded array S1X60000 series epson 99 design guide (3) 2.0 v specifications (v dd = 1.8 to 2.2 v, t a = -40 to +85c) table 6-13 1 port/2 port ram read cycle (1/8) ram1p1/ ram2p1 ram1p2/ ram2p2 ram1p3/ ram2p3 ram1p4/ ram2p4 parameter signal min. max. min. max. min. max. min. max. unit read cycle t rc 6.804 ? 7.736 ? 8.134 ? 9.109 ? address access time t acc ? 6.804 ? 7.736 ? 8.134 ? 9.109 cs access time t acs ? 6.804 ? 7.736 ? 8.134 ? 9.109 rw access time t arw ? 6.804 ? 7.736 ? 8.134 ? 9.109 cs active time t rcs 6.804 ? 7.736 ? 8.134 ? 9.109 ? output hold time after address change t oh 0.182 ? 0.257 ? 0.332 ? 0.407 ? output hold time after cs disable t ohcs 0.182 ? 0.257 ? 0.332 ? 0.407 ? output hold time after rw disable t ohrw 0.182 ? 0.257 ? 0.332 ? 0.407 ? ns table 6-13 1 port/2 port ram read cycle (2/8) ram1p5/ ram2p5 ram1p6/ ram2p6 ram1p7/ ram2p7 ram1p8/ ram2p8 parameter signal min. max. min. max. min. max. min. max. unit read cycle t rc 8.450 ? 9.382 ? 9.781 ? 10.755 ? address access time t acc ? 8.450 ? 9.382 ? 9.781 ? 10.755 cs access time t acs ? 8.450 ? 9.382 ? 9.781 ? 10.755 rw access time t arw ? 8.450 ? 9.382 ? 9.781 ? 10.755 cs active time t rcs 8.450 ? 9.382 ? 9.781 ? 10.755 ? output hold time after address change t oh 0.182 ? 0.257 ? 0.332 ? 0.407 ? output hold time after cs disable t ohcs 0.182 ? 0.257 ? 0.332 ? 0.407 ? output hold time after rw disable t ohrw 0.182 ? 0.257 ? 0.332 ? 0.407 ? ns chapter 6 memory blocks 100 epson embedded array S1X60000 series design guide (3) 2.0 v specifications (v dd = 1.8 to 2.2 v, t a = -40 to +85c) table 6-13 1 port/2 port ram read cycle (3/8) ram1p9/ ram2p9 ram1p10/ ram2p10 ram1p11/ ram2p11 ram1p12/ ram2p12 parameter signal min. max. min. max. min. max. min. max. unit read cycle t rc 10.096 ? 11.028 ? 11.427 ? 12.402 ? address access time t acc ? 10.096 ? 11.028 ? 11.427 ? 12.402 cs access time t acs ? 10.096 ? 11.028 ? 11.427 ? 12.402 rw access time t arw ? 10.096 ? 11.028 ? 11.427 ? 12.402 cs active time t rcs 10.096 ? 11.028 ? 11.427 ? 12.402 ? output hold time after address change t oh 0.182 ? 0.257 ? 0.332 ? 0.407 ? output hold time after cs disable t ohcs 0.182 ? 0.257 ? 0.332 ? 0.407 ? output hold time after rw disable t ohrw 0.182 ? 0.257 ? 0.332 ? 0.407 ? ns table 6-13 1 port/2 port ram read cycle (4/8) ram1p13/ ram2p13 ram1p14/ ram2p14 ram1p15/ ram2p15 ram1p16/ ram2p16 parameter signal min. max. min. max. min. max. min. max. unit read cycle t rc 11.743 ? 12.675 ? 13.074 ? 14.048 ? address access time t acc ? 11.743 ? 12.675 ? 13.074 ? 14.048 cs access time t acs ? 11.743 ? 12.675 ? 13.074 ? 14.048 rw access time t arw ? 11.743 ? 12.675 ? 13.074 ? 14.048 cs active time t rcs 11.743 ? 12.675 ? 13.074 ? 14.048 ? output hold time after address change t oh 0.182 ? 0.257 ? 0.332 ? 0.407 ? output hold time after cs disable t ohcs 0.182 ? 0.257 ? 0.332 ? 0.407 ? output hold time after rw disable t ohrw 0.182 ? 0.257 ? 0.332 ? 0.407 ? ns chapter 6 memory blocks embedded array S1X60000 series epson 101 design guide (3) 2.0 v specifications (v dd = 1.8 to 2.2 v, t a = -40 to +85c) table 6-13 1 port/2 port ram read cycle (5/8) ram1p17/ ram2p17 ram1p18/ ram2p18 ram1p19/ ram2p19 ram1p20/ ram2p20 parameter signal min. max. min. max. min. max. min. max. unit read cycle t rc 13.389 ? 14.321 ? 14.720 ? 15.694 ? address access time t acc ? 13.389 ? 14.321 ? 14.720 ? 15.694 cs access time t acs ? 13.389 ? 14.321 ? 14.720 ? 15.694 rw access time t arw ? 13.389 ? 14.321 ? 14.720 ? 15.694 cs active time t rcs 13.389 ? 14.321 ? 14.720 ? 15.694 ? output hold time after address change t oh 0.182 ? 0.257 ? 0.332 ? 0.407 ? output hold time after cs disable t ohcs 0.182 ? 0.257 ? 0.332 ? 0.407 ? output hold time after rw disable t ohrw 0.182 ? 0.257 ? 0.332 ? 0.407 ? ns table 6-13 1 port/2 port ram read cycle (6/8) ram1p21/ ram2p21 ram1p22/ ram2p22 ram1p23/ ram2p23 ram1p24/ ram2p24 parameter signal min. max. min. max. min. max. min. max. unit read cycle t rc 15.036 ? 15.967 ? 16.366 ? 17.341 ? address access time t acc ? 15.036 ? 15.967 ? 16.366 ? 17.341 cs access time t acs ? 15.036 ? 15.967 ? 16.366 ? 17.341 rw access time t arw ? 15.036 ? 15.967 ? 16.366 ? 17.341 cs active time t rcs 15.036 ? 15.967 ? 16.366 ? 17.341 ? output hold time after address change t oh 0.182 ? 0.257 ? 0.332 ? 0.407 ? output hold time after cs disable t ohcs 0.182 ? 0.257 ? 0.332 ? 0.407 ? output hold time after rw disable t ohrw 0.182 ? 0.257 ? 0.332 ? 0.407 ? ns chapter 6 memory blocks 102 epson embedded array S1X60000 series design guide (3) 2.0 v specifications (v dd = 1.8 to 2.2 v, t a = -40 to +85c) table 6-13 1 port/2 port ram read cycle (7/8) ram1p25/ ram2p25 ram1p26/ ram2p26 ram1p27/ ram2p27 ram1p28/ ram2p28 parameter signal min. max. min. max. min. max. min. max. unit read cycle t rc 16.682 ? 17.614 ? 18.013 ? 18.987 ? address access time t acc ? 16.682 ? 17.614 ? 18.013 ? 18.987 cs access time t acs ? 16.682 ? 17.614 ? 18.013 ? 18.987 rw access time t arw ? 16.682 ? 17.614 ? 18.013 ? 18.987 cs active time t rcs 16.682 ? 17.614 ? 18.013 ? 18.987 ? output hold time after address change t oh 0.182 ? 0.257 ? 0.332 ? 0.407 ? output hold time after cs disable t ohcs 0.182 ? 0.257 ? 0.332 ? 0.407 ? output hold time after rw disable t ohrw 0.182 ? 0.257 ? 0.332 ? 0.407 ? ns table 6-13 1 port/2 port ram read cycle (8/8) ram1p29/ ram2p29 ram1p30/ ram2p30 ram1p31/ ram2p31 ram1p32/ ram2p32 parameter signal min. max. min. max. min. max. min. max. unit read cycle t rc 18.328 ? 19.260 ? 19.659 ? 20.633 ? address access time t acc ? 18.328 ? 19.260 ? 19.659 ? 20.633 cs access time t acs ? 18.328 ? 19.260 ? 19.659 ? 20.633 rw access time t arw ? 18.328 ? 19.260 ? 19.659 ? 20.633 cs active time t rcs 18.328 ? 19.260 ? 19.659 ? 20.633 ? output hold time after address change t oh 0.182 ? 0.257 ? 0.332 ? 0.407 ? output hold time after cs disable t ohcs 0.182 ? 0.257 ? 0.332 ? 0.407 ? output hold time after rw disable t ohrw 0.182 ? 0.257 ? 0.332 ? 0.407 ? ns chapter 6 memory blocks embedded array S1X60000 series epson 103 design guide (3) 2.0 v specifications (v dd = 1.8 to 2.2 v, t a = -40 to +85c) table 6-14 1 port/2 port ram write cycle (1/8) ram1p1/ ram2p1 ram1p2/ ram2p2 ram1p3/ ram2p3 ram1p4/ ram2p4 parameter signal min. max. min. max. min. max. min. max. unit write cycle t wc 4.807 ? 6.341 ? 7.878 ? 9.413 ? write pulse width t wp 2.720 ? 4.254 ? 5.791 ? 7.326 ? cs active time t wcs 2.720 ? 4.254 ? 5.791 ? 7.326 ? address setup time t as 0.696 ? 0.696 ? 0.696 ? 0.696 ? address hold time t ah 1.391 ? 1.391 ? 1.391 ? 1.391 ? data setup time t ds 0.000 ? 0.000 ? 0.000 ? 0.000 ? data hold time t dh 2.652 ? 3.712 ? 4.773 ? 5.834 ? ns table 6-14 1 port/2 port ram write cycle (2/8) ram1p5/ ram2p5 ram1p6/ ram2p6 ram1p7/ ram2p7 ram1p8/ ram2p8 parameter signal min. max. min. max. min. max. min. max. unit write cycle t wc 5.008 ? 6.542 ? 8.079 ? 9.614 ? write pulse width t wp 2.822 ? 4.356 ? 5.893 ? 7.428 ? cs active time t wcs 2.822 ? 4.356 ? 5.893 ? 7.428 ? address setup time t as 0.795 ? 0.795 ? 0.795 ? 0.795 ? address hold time t ah 1.391 ? 1.391 ? 1.391 ? 1.391 ? data setup time t ds 0.000 ? 0.000 ? 0.000 ? 0.000 ? data hold time t dh 2.744 ? 3.804 ? 4.866 ? 5.926 ? ns chapter 6 memory blocks 104 epson embedded array S1X60000 series design guide (3) 2.0 v specifications (v dd = 1.8 to 2.2 v, t a = -40 to +85c) table 6-14 1 port/2 port ram write cycle (3/8) ram1p9/ ram2p9 ram1p10/ ram2p10 ram1p11/ ram2p11 ram1p12/ ram2p12 parameter signal min. max. min. max. min. max. min. max. unit write cycle t wc 5.238 ? 6.772 ? 8.309 ? 9.844 ? write pulse width t wp 2.953 ? 4.487 ? 6.024 ? 7.559 ? cs active time t wcs 2.953 ? 4.487 ? 6.024 ? 7.559 ? address setup time t as 0.894 ? 0.894 ? 0.894 ? 0.894 ? address hold time t ah 1.391 ? 1.391 ? 1.391 ? 1.391 ? data setup time t ds 0.000 ? 0.000 ? 0.000 ? 0.000 ? data hold time t dh 2.836 ? 3.897 ? 4.958 ? 6.019 ? ns table 6-14 1 port/2 port ram write cycle (4/8) ram1p13/ ram2p13 ram1p14/ ram2p14 ram1p15/ ram2p15 ram1p16/ ram2p16 parameter signal min. max. min. max. min. max. min. max. unit write cycle t wc 5.497 ? 7.031 ? 8.568 ? 10.103 ? write pulse width t wp 3.113 ? 4.647 ? 6.184 ? 7.719 ? cs active time t wcs 3.113 ? 4.647 ? 6.184 ? 7.719 ? address setup time t as 0.993 ? 0.993 ? 0.993 ? 0.993 ? address hold time t ah 1.391 ? 1.391 ? 1.391 ? 1.391 ? data setup time t ds 0.000 ? 0.000 ? 0.000 ? 0.000 ? data hold time t dh 2.928 ? 3.989 ? 5.050 ? 6.111 ? ns chapter 6 memory blocks embedded array S1X60000 series epson 105 design guide (3) 2.0 v specifications (v dd = 1.8 to 2.2 v, t a = -40 to +85c) table 6-14 1 port/2 port ram write cycle (5/8) ram1p17/ ram2p17 ram1p18/ ram2p18 ram1p19/ ram2p19 ram1p20/ ram2p20 parameter signal min. max. min. max. min. max. min. max. unit write cycle t wc 5.711 ? 7.245 ? 8.752 ? 10.317 ? write pulse width t wp 3.223 ? 4.757 ? 6.294 ? 7.829 ? cs active time t wcs 3.223 ? 4.757 ? 6.294 ? 7.829 ? address setup time t as 1.097 ? 1.097 ? 1.097 ? 1.097 ? address hold time t ah 1.391 ? 1.391 ? 1.391 ? 1.391 ? data setup time t ds 0.000 ? 0.000 ? 0.000 ? 0.000 ? data hold time t dh 3.009 ? 4.069 ? 5.131 ? 6.191 ? ns table 6-14 1 port/2 port ram write cycle (6/8) ram1p21/ ram2p21 ram1p22/ ram2p22 ram1p23/ ram2p23 ram1p24/ ram2p24 parameter signal min. max. min. max. min. max. min. max. unit write cycle t wc 5.941 ? 7.475 ? 9.012 ? 10.547 ? write pulse width t wp 3.353 ? 4.887 ? 6.424 ? 7.959 ? cs active time t wcs 3.353 ? 4.887 ? 6.424 ? 7.959 ? address setup time t as 1.197 ? 1.197 ? 1.197 ? 1.197 ? address hold time t ah 1.391 ? 1.391 ? 1.391 ? 1.391 ? data setup time t ds 0.000 ? 0.000 ? 0.000 ? 0.000 ? data hold time t dh 3.098 ? 4.159 ? 5.220 ? 6.281 ? ns chapter 6 memory blocks 106 epson embedded array S1X60000 series design guide (3) 2.0 v specifications (v dd = 1.8 to 2.2 v, t a = -40 to +85c) table 6-14 1 port/2 port ram write cycle (7/8) ram1p25/ ram2p25 ram1p26/ ram2p26 ram1p27/ ram2p27 ram1p28/ ram2p28 parameter signal min. max. min. max. min. max. min. max. unit write cycle t wc 6.171 ? 7.705 ? 9.242 ? 10.777 ? write pulse width t wp 3.483 ? 5.017 ? 6.554 ? 8.089 ? cs active time t wcs 3.483 ? 5.017 ? 6.554 ? 8.089 ? address setup time t as 1.297 ? 1.297 ? 1.297 ? 1.297 ? address hold time t ah 1.391 ? 1.391 ? 1.391 ? 1.391 ? data setup time t ds 0.000 ? 0.000 ? 0.000 ? 0.000 ? data hold time t dh 3.188 ? 4.249 ? 5.310 ? 6.371 ? ns table 6-14 1 port/2 port ram write cycle (8/8) ram1p29/ ram2p29 ram1p30/ ram2p30 ram1p31/ ram2p31 ram1p32/ ram2p32 parameter signal min. max. min. max. min. max. min. max. unit write cycle t wc 6.400 ? 7.934 ? 9.471 ? 11.006 ? write pulse width t wp 3.613 ? 5.147 ? 6.684 ? 8.219 ? cs active time t wcs 3.613 ? 5.147 ? 6.684 ? 8.219 ? address setup time t as 1.396 ? 1.396 ? 1.396 ? 1.396 ? address hold time t ah 1.391 ? 1.391 ? 1.391 ? 1.391 ? data setup time t ds 0.000 ? 0.000 ? 0.000 ? 0.000 ? data hold time t dh 3.278 ? 4.339 ? 5.400 ? 6.461 ? ns chapter 6 memory blocks embedded array S1X60000 series epson 107 design guide (4) 2.0 v specifications (v dd = 1.8 to 2.2 v, t a = 0 to +70c) table 6-15 1 port/2 port ram read cycle (1/8) ram1p1/ ram2p1 ram1p2/ ram2p2 ram1p3/ ram2p3 ram1p4/ ram2p4 parameter signal min. max. min. max. min. max. min. max. unit read cycle t rc 6.455 ? 7.339 ? 7.717 ? 8.642 ? address access time t acc ? 6.455 ? 7.339 ? 7.717 ? 8.642 cs access time t acs ? 6.455 ? 7.339 ? 7.717 ? 8.642 rw access time t arw ? 6.455 ? 7.339 ? 7.717 ? 8.642 cs active time t rcs 6.455 ? 7.339 ? 7.717 ? 8.642 ? output hold time after address change t oh 0.192 ? 0.271 ? 0.351 ? 0.430 ? output hold time after cs disable t ohcs 0.192 ? 0.271 ? 0.351 ? 0.430 ? output hold time after rw disable t ohrw 0.192 ? 0.271 ? 0.351 ? 0.430 ? ns table 6-15 1 port/2 port ram read cycle (2/8) ram1p5/ ram2p5 ram1p6/ ram2p6 ram1p7/ ram2p7 ram1p8/ ram2p8 parameter signal min. max. min. max. min. max. min. max. unit read cycle t rc 8.017 ? 8.901 ? 9.279 ? 10.204 ? address access time t acc ? 8.017 ? 8.901 ? 9.279 ? 10.204 cs access time t acs ? 8.017 ? 8.901 ? 9.279 ? 10.204 rw access time t arw ? 8.017 ? 8.901 ? 9.279 ? 10.204 cs active time t rcs 8.017 ? 8.901 ? 9.279 ? 10.204 ? output hold time after address change t oh 0.192 ? 0.271 ? 0.351 ? 0.430 ? output hold time after cs disable t ohcs 0.192 ? 0.271 ? 0.351 ? 0.430 ? output hold time after rw disable t ohrw 0.192 ? 0.271 ? 0.351 ? 0.430 ? ns chapter 6 memory blocks 108 epson embedded array S1X60000 series design guide (4) 2.0 v specifications (v dd = 1.8 to 2.2 v, t a = 0 to +70c) table 6-15 1 port/2 port ram read cycle (3/8) ram1p9/ ram2p9 ram1p10/ ram2p10 ram1p11/ ram2p11 ram1p12/ ram2p12 parameter signal min. max. min. max. min. max. min. max. unit read cycle t rc 9.579 ? 10.463 ? 10.841 ? 11.766 ? address access time t acc ? 9.579 ? 10.463 ? 10.841 ? 11.766 cs access time t acs ? 9.579 ? 10.463 ? 10.841 ? 11.766 rw access time t arw ? 9.579 ? 10.463 ? 10.841 ? 11.766 cs active time t rcs 9.579 ? 10.463 ? 10.841 ? 11.766 ? output hold time after address change t oh 0.192 ? 0.271 ? 0.351 ? 0.430 ? output hold time after cs disable t ohcs 0.192 ? 0.271 ? 0.351 ? 0.430 ? output hold time after rw disable t ohrw 0.192 ? 0.271 ? 0.351 ? 0.430 ? ns table 6-15 1 port/2 port ram read cycle (4/8) ram1p13/ ram2p13 ram1p14/ ram2p14 ram1p15/ ram2p15 ram1p16/ ram2p16 parameter signal min. max. min. max. min. max. min. max. unit read cycle t rc 11.141 ? 12.025 ? 12.403 ? 13.328 ? address access time t acc ? 11.141 ? 12.025 ? 12.403 ? 13.328 cs access time t acs ? 11.141 ? 12.025 ? 12.403 ? 13.328 rw access time t arw ? 11.141 ? 12.025 ? 12.403 ? 13.328 cs active time t rcs 11.141 ? 12.025 ? 12.403 ? 13.328 ? output hold time after address change t oh 0.192 ? 0.271 ? 0.351 ? 0.430 ? output hold time after cs disable t ohcs 0.192 ? 0.271 ? 0.351 ? 0.430 ? output hold time after rw disable t ohrw 0.192 ? 0.271 ? 0.351 ? 0.430 ? ns chapter 6 memory blocks embedded array S1X60000 series epson 109 design guide (4) 2.0 v specifications (v dd = 1.8 to 2.2 v, t a = 0 to +70c) table 6-15 1 port/2 port ram read cycle (5/8) ram1p17/ ram2p17 ram1p18/ ram2p18 ram1p19/ ram2p19 ram1p20/ ram2p20 parameter signal min. max. min. max. min. max. min. max. unit read cycle t rc 12.703 ? 13.587 ? 13.965 ? 14.889 ? address access time t acc ? 12.703 ? 13.587 ? 13.965 ? 14.889 cs access time t acs ? 12.703 ? 13.587 ? 13.965 ? 14.889 rw access time t arw ? 12.703 ? 13.587 ? 13.965 ? 14.889 cs active time t rcs 12.703 ? 13.587 ? 13.965 ? 14.889 ? output hold time after address change t oh 0.192 ? 0.271 ? 0.351 ? 0.430 ? output hold time after cs disable t ohcs 0.192 ? 0.271 ? 0.351 ? 0.430 ? output hold time after rw disable t ohrw 0.192 ? 0.271 ? 0.351 ? 0.430 ? ns table 6-15 1 port/2 port ram read cycle (6/8) ram1p21/ ram2p21 ram1p22/ ram2p22 ram1p23/ ram2p23 ram1p24/ ram2p24 parameter signal min. max. min. max. min. max. min. max. unit read cycle t rc 14.264 ? 15.149 ? 15.527 ? 16.451 ? address access time t acc ? 14.264 ? 15.149 ? 15.527 ? 16.451 cs access time t acs ? 14.264 ? 15.149 ? 15.527 ? 16.451 rw access time t arw ? 14.264 ? 15.149 ? 15.527 ? 16.451 cs active time t rcs 14.264 ? 15.149 ? 15.527 ? 16.451 ? output hold time after address change t oh 0.192 ? 0.271 ? 0.351 ? 0.430 ? output hold time after cs disable t ohcs 0.192 ? 0.271 ? 0.351 ? 0.430 ? output hold time after rw disable t ohrw 0.192 ? 0.271 ? 0.351 ? 0.430 ? ns chapter 6 memory blocks 110 epson embedded array S1X60000 series design guide (4) 2.0 v specifications (v dd = 1.8 to 2.2 v, t a = 0 to +70c) table 6-15 1 port/2 port ram read cycle (7/8) ram1p25/ ram2p25 ram1p26/ ram2p26 ram1p27/ ram2p27 ram1p28/ ram2p28 parameter signal min. max. min. max. min. max. min. max. unit read cycle t rc 15.826 ? 16.711 ? 17.089 ? 18.013 ? address access time t acc ? 15.826 ? 16.711 ? 17.089 ? 18.013 cs access time t acs ? 15.826 ? 16.711 ? 17.089 ? 18.013 rw access time t arw ? 15.826 ? 16.711 ? 17.089 ? 18.013 cs active time t rcs 15.826 ? 16.711 ? 17.089 ? 18.013 ? output hold time after address change t oh 0.192 ? 0.271 ? 0.351 ? 0.430 ? output hold time after cs disable t ohcs 0.192 ? 0.271 ? 0.351 ? 0.430 ? output hold time after rw disable t ohrw 0.192 ? 0.271 ? 0.351 ? 0.430 ? ns table 6-15 1 port/2 port ram read cycle (8/8) ram1p29/ ram2p29 ram1p30/ ram2p30 ram1p31/ ram2p31 ram1p32/ ram2p32 parameter signal min. max. min. max. min. max. min. max. unit read cycle t rc 17.388 ? 18.272 ? 18.651 ? 19.575 ? address access time t acc ? 17.388 ? 18.272 ? 18.651 ? 19.575 cs access time t acs ? 17.388 ? 18.272 ? 18.651 ? 19.575 rw access time t arw ? 17.388 ? 18.272 ? 18.651 ? 19.575 cs active time t rcs 17.388 ? 18.272 ? 18.651 ? 19.575 ? output hold time after address change t oh 0.192 ? 0.271 ? 0.351 ? 0.430 ? output hold time after cs disable t ohcs 0.192 ? 0.271 ? 0.351 ? 0.430 ? output hold time after rw disable t ohrw 0.192 ? 0.271 ? 0.351 ? 0.430 ? ns chapter 6 memory blocks embedded array S1X60000 series epson 111 design guide (4) 2.0 v specifications (v dd = 1.8 to 2.2 v, t a = 0 to +70c) table 6-16 1 port/2 port ram write cycle (1/8) ram1p1/ ram2p1 ram1p2/ ram2p2 ram1p3/ ram2p3 ram1p4/ ram2p4 parameter signal min. max. min. max. min. max. min. max. unit write cycle t wc 4.560 ? 6.016 ? 7.474 ? 8.930 ? write pulse width t wp 2.580 ? 4.036 ? 5.494 ? 6.950 ? cs active time t wcs 2.580 ? 4.036 ? 5.494 ? 6.950 ? address setup time t as 0.661 ? 0.661 ? 0.661 ? 0.661 ? address hold time t v 1.319 ? 1.319 ? 1.319 ? 1.319 ? data setup time t ds 0.000 ? 0.000 ? 0.000 ? 0.000 ? data hold time t dh 2.516 ? 3.522 ? 4.529 ? 5.535 ? ns table 6-16 1 port/2 port ram write cycle (2/8) ram1p5/ ram2p5 ram1p6/ ram2p6 ram1p7/ ram2p7 ram1p8/ ram2p8 parameter signal min. max. min. max. min. max. min. max. unit write cycle t wc 4.750 ? 6.206 ? 7.664 ? 9.120 ? write pulse width t wp 2.677 ? 4.133 ? 5.591 ? 7.047 ? cs active time t wcs 2.677 ? 4.133 ? 5.591 ? 7.047 ? address setup time t as 0.754 ? 0.754 ? 0.754 ? 0.754 ? address hold time t v 1.319 ? 1.319 ? 1.319 ? 1.319 ? data setup time t ds 0.000 ? 0.000 ? 0.000 ? 0.000 ? data hold time t dh 2.603 ? 3.609 ? 4.616 ? 5.623 ? ns chapter 6 memory blocks 112 epson embedded array S1X60000 series design guide (4) 2.0 v specifications (v dd = 1.8 to 2.2 v, t a = 0 to +70c) table 6-16 1 port/2 port ram write cycle (3/8) ram1p9/ ram2p9 ram1p10/ ram2p10 ram1p11/ ram2p11 ram1p12/ ram2p12 parameter signal min. max. min. max. min. max. min. max. unit write cycle t wc 4.969 ? 6.424 ? 7.882 ? 9.338 ? write pulse width t wp 2.802 ? 4.257 ? 5.715 ? 7.171 ? cs active time t wcs 2.802 ? 4.257 ? 5.715 ? 7.171 ? address setup time t as 0.848 ? 0.848 ? 0.848 ? 0.848 ? address hold time t ah 1.319 ? 1.319 ? 1.319 ? 1.319 ? data setup time t ds 0.000 ? 0.000 ? 0.000 ? 0.000 ? data hold time t dh 2.691 ? 3.697 ? 4.704 ? 5.710 ? ns table 6-16 1 port/2 port ram write cycle (4/8) ram1p13/ ram2p13 ram1p14/ ram2p14 ram1p15/ ram2p15 ram1p16/ ram2p16 parameter signal min. max. min. max. min. max. min. max. unit write cycle t wc 5.214 ? 6.670 ? 8.128 ? 9.584 ? write pulse width t wp 2.953 ? 4.409 ? 5.867 ? 7.323 ? cs active time t wcs 2.953 ? 4.409 ? 5.867 ? 7.323 ? address setup time t as 0.942 ? 0.942 ? 0.942 ? 0.942 ? address hold time t ah 1.319 ? 1.319 ? 1.319 ? 1.319 ? data setup time t ds 0.000 ? 0.000 ? 0.000 ? 0.000 ? data hold time t dh 2.778 ? 3.784 ? 4.791 ? 5.798 ? ns chapter 6 memory blocks embedded array S1X60000 series epson 113 design guide (4) 2.0 v specifications (v dd = 1.8 to 2.2 v, t a = 0 to +70c) table 6-16 1 port/2 port ram write cycle (5/8) ram1p17/ ram2p17 ram1p18/ ram2p18 ram1p19/ ram2p19 ram1p20/ ram2p20 parameter signal min. max. min. max. min. max. min. max. unit write cycle t wc 5,418 ? 6.873 ? 8.331 ? 9.788 ? write pulse width t wp 3.058 ? 4.513 ? 5,971 ? 7.428 ? cs active time t wcs 3.058 ? 4.513 ? 5,971 ? 7.428 ? address setup time t as 1.041 ? 1.041 ? 1.041 ? 1.041 ? address hold time t ah 1.319 ? 1.319 ? 1.319 ? 1.319 ? data setup time t ds 0.000 ? 0.000 ? 0.000 ? 0.000 ? data hold time t dh 2.854 ? 3.860 ? 4.867 ? 5.874 ? ns table 6-16 1 port/2 port ram write cycle (6/8) ram1p21/ ram2p21 ram1p22/ ram2p22 ram1p23/ ram2p23 ram1p24/ ram2p24 parameter signal min. max. min. max. min. max. min. max. unit write cycle t wc 5.635 ? 7.091 ? 8.549 ? 10.005 ? write pulse width t wp 3.181 ? 4.637 ? 6.095 ? 7.551 ? cs active time t wcs 3.181 ? 4.637 ? 6.095 ? 7.551 ? address setup time t as 1.135 ? 1.135 ? 1.135 ? 1.135 ? address hold time t ah 1.319 ? 1.319 ? 1.319 ? 1.319 ? data setup time t ds 0.000 ? 0.000 ? 0.000 ? 0.000 ? data hold time t dh 2.940 ? 3.946 ? 4.953 ? 5.959 ? ns chapter 6 memory blocks 114 epson embedded array S1X60000 series design guide (4) 2.0 v specifications (v dd = 1.8 to 2.2 v, t a = 0 to +70c) table 6-16 1 port/2 port ram write cycle (7/8) ram1p25/ ram2p25 ram1p26/ ram2p26 ram1p27/ ram2p27 ram1p28/ ram2p28 parameter signal min. max. min. max. min. max. min. max. unit write cycle t wc 5.853 ? 7.309 ? 8.767 ? 10.223 ? write pulse width t wp 3.304 ? 4.760 ? 6.218 ? 7.674 ? cs active time tv 3.304 ? 4.760 ? 6.218 ? 7.674 ? address setup time tv 1.230 ? 1.230 ? 1.230 ? 1.230 ? address hold time t ah 1.319 ? 1.319 ? 1.319 ? 1.319 ? data setup time t ds 0.000 ? 0.000 ? 0.000 ? 0.000 ? data hold time tv 3.025 ? 4.031 ? 5.038 ? 6.044 ? ns table 6-16 1 port/2 port ram write cycle (8/8) ram1p29/ ram2p29 ram1p30/ ram2p30 ram1p31/ ram2p31 ram1p32/ ram2p32 parameter signal min. max. min. max. min. max. min. max. unit write cycle t wc 6.071 ? 7.527 ? 8.985 ? 10.441 ? write pulse width t wp 3.427 ? 4.883 ? 6.341 ? 7.797 ? cs active time t wcs 3.427 ? 4.883 ? 6.341 ? 7.797 ? address setup time t as 1.325 ? 1.325 ? 1.325 ? 1.325 ? address hold time t ah 1.319 ? 1.319 ? 1.319 ? 1.319 ? data setup time t d s 0.000 ? 0.000 ? 0.000 ? 0.000 ? data hold time t dh 3.110 ? 4.116 ? 5.123 ? 6.130 ? ns chapter 6 memory blocks embedded array S1X60000 series epson 115 design guide 6.1.7 timing charts (1) 1 port ram t oh xx x x t ohcs t acs t acc t acc t ohrw t arw a1 a2 a3 address cs rw data out t rcs t rc a1 a1 a2 a3 a3 figure 6-2 read cycle t wc t as t wp t dh t ah address cs rw data in valid t ds figure 6-3 write cycle (rw control) t wc t as t wcs t dh t ah address cs rw data in valid t ds figure 6-4 write cycle (cs control) chapter 6 memory blocks 116 epson embedded array S1X60000 series design guide (2) 2 port ram t oh xx x x t ohcs t acs t acc t acc t ohrw t arw a1 a2 a3 address cs rd data out t rcs t rc a1 a1 a2 a3 a3 figure 6-5 read cycle t wc t as t wp t dh t ah address cs wr data in valid t ds figure 6-6 write cycle (wr control) t wc t as t wcs t dh t ah address cs wr data in valid t ds figure 6-7 write cycle (cs control) chapter 6 memory blocks embedded array S1X60000 series epson 117 design guide 6.2 basic cell type ram (synchronous type) the S1X60000 series supports clock synchronous ram, in addition to the clock asynchronous ram described in 6.1. this type of ram has latches in its chip select, write enable, address, and data input parts, allowing for clock synchronized, high-speed operation. 6.2.1 features ? clock synchronous 1 port and 2 port ram are available. ? memory contain latches in the chip select, write enable, address, and data input parts, allowing for clock synchronized, high speed operation. ? the data input and the data output ports are separated. ? words can be configured from 16 to 256 words in 4-word increments, while bits can be configured between 1 to 32 bits in 1-bit increments. ? maximum configuration: 8 kbits per module 6.2.2 word/bit configurations and cell names of the ram the delay parameters of the clock synchronous ram vary with its word/bit configurations. therefore, epson has cells corresponding to available individual word/bit configurations. when using the clock synchronous ram, please inform epson whether the ram used is 1 port or 2 port and how it is word/bit configured. the cell names available for the typical word/bit configurations of 1 port and 2 port ram sticks are listed on tables 6-17 and 6-18, respectively. the cell names for synchronous ram sticks are assigned by the naming rules described below according to the word/bit configurations. 1 port ram ?sj xxx yy? 2 port ram ?sk xxx yy? xxx: number of words (hex), yy: number of bits (hex) if any synchronous ram whose word/bit configurations exceed the acceptable range is required, use multiple instances of synchronous ram in combination as needed for the intended application. table 6-17 cell names available for various word/bit configurations of 1 port ram (clock synchronous type) 64 word 128 word 192 word 256 word 8 bit sj04008 sj08008 sj0c008 sj10008 16 bit sj04010 sj08010 sj0c010 sj10010 24 bit sj04018 sj08018 sj0c018 sj10018 32 bit sj04020 sj08020 sj0c020 sj10020 chapter 6 memory blocks 118 epson embedded array S1X60000 series design guide table 6-18 cell names available for various word/bit configurations of 2 port ram (clock synchronous type) 64 word 128 word 192 word 256 word 8 bit sk04008 sk08008 sk0c008 sk10008 16 bit sk04010 sk08010 sk0c010 sk10010 24 bit sk04018 sk08018 sk0c018 sk10018 32 bit sk04020 sk08020 sk0c020 sk10020 6.2.3 ram sizes the ram sizes in the x and y directions and the number of basic cells used are calculated using the following equations, respectively. (1) 1 port ram size in x direction: rx = 27 + 7 number of words / 4 + 8 size in y direction: ry = + 7 number of bits 2 + 2 number of basic cells: rambcs=rx ry note that = 3 when 16 number of words 32, or 4 when 36 number of words 256. table 6-19 typical configuration of 1 port ram and number of basic cells 8 bit 16 bit 24 bit 32 bit 32 word 2,548 4,004 5,460 6,916 64 word 4,263 6,615 8,967 11,319 128 word 7,511 11,655 15,799 19,943 256 word 14,007 21,735 29,463 37,191 (2) 2 port ram size in x direction: rx = 24 + 7 number of words / 4 + 8 size in y direction: ry = + 7 number of bits 2 + 2 number of basic cells: rambcs=rx ry note that = 4 when 16 number of words 32, or 6 when 36 number of words 256. table 6-20 typical configuration of 2 port ram and number of basic cells 8bit 16bit 24bit 32bit 32word 2,552 3,960 5,368 6,776 64word 4,464 6,768 9,072 11,376 128word 7,936 12,032 16,128 20,224 256word 14,880 22,560 30,240 37,920 6.2.4 investigating ram placement on master slice to determine whether the ram (clock synchronous type) can be mounted on each master, refer to the description in section 6.1.4. chapter 6 memory blocks embedded array S1X60000 series epson 119 design guide 6.2.5 functional description 6.2.5.1 1 port ram (clock synchronous type) (1) input/output signals and block diagram table 6-21 signal description of a 1 port ram (clock synchronous type) input/output signal symbol name description ck clock input the rising edge (l(h) on the clock input (ck) latches chip select (xcs), write enable (xwe), address inputs (a0 to an), and data inputs (d0 to dn) into the internal logic of the ram. xcs chip select latched by the rising edge on the clock input (ck). when xcs is latched low, chip select is enabled. xwe write enable latched by the rising edge on the clock input (ck). when xwe is latched low, write is enabled; when high, read is enabled. a0 to an address input latched by the rising edge on the clock input (ck). d0 to dn data input latched by the rising edge on the clock input (ck). the data is written into memory cells when write enable (xwe) = low. y0 to yn data output during readout, the data from memory cells are output after a specified access time has elapsed from the rising edge on the clock input (ck). during write, the write data is output from these pins synchronously with the ck. therefore, note that during the writing of data, previously read data is not retained. data i/o buffer memory cell array data i/o buffer memory cell array data i/o buffer memory cell array address buffer control row decoder dn yn d1 y1 d0 y0 a0 an a2 a1 ck xcs xwe figure 6-8 block diagram of a 1 port ram (clock synchronous type) chapter 6 memory blocks 120 epson embedded array S1X60000 series design guide (2) circuit operation to write to the ram, enable (l) chip select (xcs) and write enable (xwe) and then setting address inputs (a0 to an) and data inputs (d0 to dn) before the clock input (ck) increases. when the clock input increases, all of the chip select, write enable, address inputs, and data inputs are latched, thereby initializing a write operation. the write data is output from the data output pins (y0 to yn) until the next time the clock input increases. to read from the ram, enable (l) chip select (xcs) and disable (h) write enable (xwe), and then setting address inputs (a0 to an) before the clock input (ck) increases. when the clock input increases, all of the chip select, write enable, and address inputs are latched, thereby initializing a read operation. during this period, data is sent out from the output pins (y0 to yn) after a specified access time has elapsed from the rising edge on the clock input. table 6-22 truth table for operation of 1 port ram (clock synchronous type) ck xcs xwe output status? operation mode l h l h read data read l h l l write data write l h h l or h data hold standby chapter 6 memory blocks embedded array S1X60000 series epson 121 design guide 6.2.5.2 2 port ram (clock synchronous type) (1) input/output signals and block diagram the first port is write only, and the second port is read only. the ram has a clock input pin for each port, which can be operated independently with given frequencies and timings. if write enable (xwa) for the first port and read enable (xrb) for the second port both are latched high, the ram is in standby. table 6-23 signal description of 2 port ram (clock synchronous type) signals for the first port (write only) input/output signal symbol name description cka clock input the rising edge (l(h) on the clock input (cka) latches write enable (xwa), address inputs (aa0 to aan), and data inputs (d0 to dn) into the internal logic of the ram. xwa write enable latched by the rising edge on the clock input (cka). when xwe is latched low, a write operation starts. aa0 to aan address input latched by the rising edge on the clock input (cka) d0 to dn data input latched by the rising edge on the clock input (cka). when write enable (xwa) = low, data is written into memory cells. signals for the second port (read only) input/output signal symbol name description ckb clock input the rising edge (l(h) on the clock input (ckb) latches read enable (xrb) and address inputs (ab0 to abn) into the internal logic of the ram. xrb read enable latched by the rising edge on the clock input (ckb). when xrb is latched low, a read operation starts. ab0 to abn address input latched by the rising edge on the clock input (ckb). y0 to yn data output data from memory cells are output, after a specified access time has elapsed, from the rising edge of the clock input (ckb). chapter 6 memory blocks 122 epson embedded array S1X60000 series design guide data i/o buffer memory cell array address buffer address buffer row decoder row decoder port 1 control port 2 control aa0 cka aa1 aa2 aan xwa ab0 ckb ab1 ab2 abn xrb y0 yn dn d0 figure 6-9 block diagram of a 2 port ram (clock synchronous type) (2) circuit operation to write to the ram, enable (l) write enable (xwa) and then setting address inputs (aa0 to aan) and data inputs (d0 to dn) before the clock input (cka) increases. when the clock input (cka) increases, all of the write enable (xwa), address inputs (aa0 to aan), and data inputs (d0 to dn) are latched, thereby initializing a write operation. to read from the ram, enable (l) read enable (xrb) and then setting address inputs (ab0 to abn) before the clock input (ckb) increases. when the clock input (ckb) increases, all of the read enable (xrb) and address inputs (ab0 to abn) are latched, thereby initializing a read operation. during this period, data is sent out from the output pins (y0 to yn), after a specified access time has elapsed, from the rising edge on the clock input (ckb). table 6-24 truth table for operation of 2 port ram (clock synchronous type) (truth table for operation of the first port (write only)) cka xwa operation mode l h h standby l h l write (truth table for operation of the second port (read only) ckb xrb output status operation mode l h h data hold standby l h l read data read if a write to and a read from are simultaneously attempted for the same memory, the write operation is given priority. data is written to the memory normally, but no result is returned for the read data request. chapter 6 memory blocks embedded array S1X60000 series epson 123 design guide 6.2.6 timing charts (1) 1 port ram ? read cycle stable stable stable t as t css t csh t wes t weh t oh t ah t ckh t acs t rcy t ckl a0 an ck xcs xwe data out old data valid data read ? write cycle t wdt t wdh data out old data valid data stable stable t as t css t csh t ah t ckh t wcy t ckl a0 an stable data in ck xcs stable t wes t weh t ds t dh xme write chapter 6 memory blocks 124 epson embedded array S1X60000 series design guide (2) 2 port ram ? first port stable stable t as t was t wah t ds t dh t ah t ckh t wcy t ckl aa0 aan stable data in cka xwa write ? second port t oh t acc stable stable t as t rbs t rbh t ah t ckh t rcy t ckl ab0 abn ckb xrb data out old data valid data read chapter 6 memory blocks embedded array S1X60000 series epson 125 design guide 6.2.7 delay parameters (1) 2.5 v specifications (v dd = 2.3 to 2.7 v, t a = -40 to +85c) 64 words 1 port/2 port ram read cycle ac characteristics table sj04008/ sk04008 sj04010/ sk04010 sj04018/ sk04018 sj04020/ sk04020 parameter symbol min. max. min. max. min. max. min. max. unit access time t acs , t acc ? 3.957 ? 4.023 ? 4.110 ? 4.193 read cycle time t rcy 3.957 ? 4.023 ? 4.110 ? 4.193 ? clock high pulse width t ckh 0.500 ? 0.500 ? 0.500 ? 0.500 ? clock low pulse width t ckl 0.500 ? 0.500 ? 0.500 ? 0.500 ? xcs setup time t css 1.000 ? 1.000 ? 1.000 ? 1.000 ? xcs hold time t csh 0.000 ? 0.000 ? 0.000 ? 0.000 ? xwe setup time t wes 1.000 ? 1.000 ? 1.000 ? 1.000 ? xwe hold time t weh 0.000 ? 0.000 ? 0.000 ? 0.000 ? xrb setup time t rbs 1.000 ? 1.000 ? 1.000 ? 1.000 ? xrb hold time t rbh 0.000 ? 0.000 ? 0.000 ? 0.000 ? address setup time t as 1.000 ? 1.000 ? 1.000 ? 1.000 ? address hold time t ah 0.000 ? 0.000 ? 0.000 ? 0.000 ? output hold time t oh 0.624 ? 0.650 ? 0.666 ? 0.680 ? ns 1 port/2 port ram write cycle ac characteristics table sj04008/ sk04008 sj04010/ sk04010 sj04018/ sk04018 sj04020/ sk04020 parameter symbol min. max. min. max. min. max. min. max. unit write cycle time t wcy 3.602 ? 3.712 ? 3.826 ? 3.940 ? clock high pulse width t ckh 0.500 ? 0.500 ? 0.500 ? 0.500 ? clock low pulse width t ckl 0.500 ? 0.500 ? 0.500 ? 0.500 ? xcs setup time t css 1.000 ? 1.000 ? 1.000 ? 1.000 ? xcs hold time t csh 0.000 ? 0.000 ? 0.000 ? 0.000 ? address setup time t as 1.000 ? 1.000 ? 1.000 ? 1.000 ? xwe setup time t wes 1.000 ? 1.000 ? 1.000 ? 1.000 ? xwe hold time t weh 0.000 ? 0.000 ? 0.000 ? 0.000 ? xwa setup time t was 1.000 ? 1.000 ? 1.000 ? 1.000 ? xwa hold time t wah 0.000 ? 0.000 ? 0.000 ? 0.000 ? address hold time t ah 0.000 ? 0.000 ? 0.000 ? 0.000 ? data hold time t dh 0.000 ? 0.000 ? 0.000 ? 0.000 ? data setup time t ds 1.000 ? 1.000 ? 1.000 ? 1.000 ? write data hold time t wdh 1.299 ? 1.338 ? 1.367 ? 1.397 ? write data through time t wdt ? 3.602 ? 3.712 ? 3.826 ? 3.940 ns chapter 6 memory blocks 126 epson embedded array S1X60000 series design guide (2) 2.5 v specifications (v dd = 2.3 to 2.7 v, t a = 0 to +70c) 64 words 1 port/2 port ram read cycle ac characteristics table sj04008/ sk04008 sj04010/ sk04010 sj04018/ sk04018 sj04020/ sk04020 parameter symbol min. max. min. max. min. max. min. max. unit access time t acs , t acc ? 3.743 ? 3.806 ? 3.887 ? 3.966 read cycle time t rcy 3.743 ? 3.806 ? 3.887 ? 3.966 ? clock high pulse width t ckh 0.500 ? 0.500 ? 0.500 ? 0.500 ? clock low pulse width t ckl 0.500 ? 0.500 ? 0.500 ? 0.500 ? xcs setup time t css 1.000 ? 1.000 ? 1.000 ? 1.000 ? xcs hold time t csh 0.000 ? 0.000 ? 0.000 ? 0.000 ? xwe setup time t wes 1.000 ? 1.000 ? 1.000 ? 1.000 ? xwe hold time t weh 0.000 ? 0.000 ? 0.000 ? 0.000 ? xrb setup time t rbs 1.000 ? 1.000 ? 1.000 ? 1.000 ? xrb hold time t rbh 0.000 ? 0.000 ? 0.000 ? 0.000 ? address setup time t as 1.000 ? 1.000 ? 1.000 ? 1.000 ? address hold time t ah 0.000 ? 0.000 ? 0.000 ? 0.000 ? output hold time t oh 0.669 ? 0.696 ? 0.713 ? 0.728 ? ns 1 port/2 port ram write cycle ac characteristics table sj04008/ sk04008 sj04010/ sk04010 sj04018/ sk04018 sj04020/ sk04020 parameter symbol min. max. min. max. min. max. min. max. unit write cycle time t wcy 3.407 ? 3.512 ? 3.619 ? 3.727 ? clock high pulse width t ckh 0.500 ? 0.500 ? 0.500 ? 0.500 ? clock low pulse width t ckl 0.500 ? 0.500 ? 0.500 ? 0.500 ? xcs setup time t css 1.000 ? 1.000 ? 1.000 ? 1.000 ? xcs hold time t csh 0.000 ? 0.000 ? 0.000 ? 0.000 ? address setup time t as 1.000 ? 1.000 ? 1.000 ? 1.000 ? xwe setup time t wes 1.000 ? 1.000 ? 1.000 ? 1.000 ? xwe hold time t weh 0.000 ? 0.000 ? 0.000 ? 0.000 ? xwa setup time t was 1.000 ? 1.000 ? 1.000 ? 1.000 ? xwa hold time t wah 0.000 ? 0.000 ? 0.000 ? 0.000 ? address hold time t ah 0.000 ? 0.000 ? 0.000 ? 0.000 ? data hold time t dh 0.000 ? 0.000 ? 0.000 ? 0.000 ? data setup time t ds 1.000 ? 1.000 ? 1.000 ? 1.000 ? write data hold time t wdh 1.391 ? 1.433 ? 1.465 ? 1.497 ? write data through time t wdt ? 3.407 ? 3.512 ? 3.619 ? 3.727 ns chapter 6 memory blocks embedded array S1X60000 series epson 127 design guide (3) 2.5 v specifications (v dd = 2.3 to 2.7 v, t a = -40 to +85c) 128 words 1 port/2 port ram read cycle ac characteristics table sj08008/ sk08008 sj08010/ sk08010 sj08018/ sk08018 sj08020/ sk08020 parameter symbol min. max. min. max. min. max. min. max. unit access time t acs , t acc ? 4.995 ? 5.060 ? 5.132 ? 5.241 read cycle time t rcy 4.995 ? 5.060 ? 5.132 ? 5.241 ? clock high pulse width t ckh 0.500 ? 0.500 ? 0.500 ? 0.500 ? clock low pulse width t ckl 0.500 ? 0.500 ? 0.500 ? 0.500 ? xcs setup time t css 1.000 ? 1.000 ? 1.000 ? 1.000 ? xcs hold time t csh 0.000 ? 0.000 ? 0.000 ? 0.000 ? xwe setup time t wes 1.000 ? 1.000 ? 1.000 ? 1.000 ? xwe hold time t weh 0.000 ? 0.000 ? 0.000 ? 0.000 ? xrb setup time t rbs 1.000 ? 1.000 ? 1.000 ? 1.000 ? xrb hold time t rbh 0.000 ? 0.000 ? 0.000 ? 0.000 ? address setup time t as 1.000 ? 1.000 ? 1.000 ? 1.000 ? address hold time t ah 0.000 ? 0.000 ? 0.000 ? 0.000 ? output hold time t oh 0.641 ? 0.659 ? 0.675 ? 0.693 ? ns 1 port/2 port ram write cycle ac characteristics table sj08008/ sk08008 sj08010/ sk08010 sj08018/ sk08018 sj08020/ sk08020 parameter symbol min. max. min. max. min. max. min. max. unit write cycle time t wcy 3.685 ? 3.807 ? 3.909 ? 4.018 ? clock high pulse width t ckh 0.500 ? 0.500 ? 0.500 ? 0.500 ? clock low pulse width t ckl 0.500 ? 0.500 ? 0.500 ? 0.500 ? xcs setup time t css 1.000 ? 1.000 ? 1.000 ? 1.000 ? xcs hold time t csh 0.000 ? 0.000 ? 0.000 ? 0.000 ? address setup time t as 1.000 ? 1.000 ? 1.000 ? 1.000 ? xwe setup time t wes 1.000 ? 1.000 ? 1.000 ? 1.000 ? xwe hold time t weh 0.000 ? 0.000 ? 0.000 ? 0.000 ? xwa setup time t was 1.000 ? 1.000 ? 1.000 ? 1.000 ? xwa hold time t wah 0.000 ? 0.000 ? 0.000 ? 0.000 ? address hold time t ah 0.000 ? 0.000 ? 0.000 ? 0.000 ? data hold time t dh 0.000 ? 0.000 ? 0.000 ? 0.000 ? data setup time t ds 1.000 ? 1.000 ? 1.000 ? 1.000 ? write data hold time t wdh 1.341 ? 1.376 ? 1.426 ? 1.433 ? write data through time t wdt ? 3.685 ? 3.807 ? 3.909 ? 4.018 ns chapter 6 memory blocks 128 epson embedded array S1X60000 series design guide (4) 2.5 v specifications (v dd = 2.3 to 2.7 v, t a = 0 to +70c) 128 words 1 port/2 port ram read cycle ac characteristics table sj08008/ sk08008 sj08010/ sk08010 sj08018/ sk08018 sj08020/ sk08020 parameter symbol min. max. min. max. min. max. min. max. unit access time t acs , t acc ? 4.725 ? 4.787 ? 4.855 ? 4.958 read cycle time t rcy 4.725 ? 4.787 ? 4.855 ? 4.958 ? clock high pulse width t ckh 0.500 ? 0.500 ? 0.500 ? 0.500 ? clock low pulse width t ckl 0.500 ? 0.500 ? 0.500 ? 0.500 ? xcs setup time t css 1.000 ? 1.000 ? 1.000 ? 1.000 ? xcs hold time t csh 0.000 ? 0.000 ? 0.000 ? 0.000 ? xwe setup time t wes 1.000 ? 1.000 ? 1.000 ? 1.000 ? xwe hold time t weh 0.000 ? 0.000 ? 0.000 ? 0.000 ? xrb setup time t rbs 1.000 ? 1.000 ? 1.000 ? 1.000 ? xrb hold time t rbh 0.000 ? 0.000 ? 0.000 ? 0.000 ? address setup time t as 1.000 ? 1.000 ? 1.000 ? 1.000 ? address hold time t ah 0.000 ? 0.000 ? 0.000 ? 0.000 ? output hold time t oh 0.686 ? 0.706 ? 0.723 ? 0.742 ? ns 1 port/2 port ram write cycle ac characteristics table sj08008/ sk08008 sj08010/ sk08010 sj08018/ sk08018 sj08020/ sk08020 parameter symbol min. max. min. max. min. max. min. max. unit write cycle time t wcy 3.486 ? 3.601 ? 3.698 ? 3.801 ? clock high pulse width t ckh 0.500 ? 0.500 ? 0.500 ? 0.500 ? clock low pulse width t ckl 0.500 ? 0.500 ? 0.500 ? 0.500 ? xcs setup time t css 1.000 ? 1.000 ? 1.000 ? 1.000 ? xcs hold time t csh 0.000 ? 0.000 ? 0.000 ? 0.000 ? address setup time t as 1.000 ? 1.000 ? 1.000 ? 1.000 ? xwe setup time t wes 1.000 ? 1.000 ? 1.000 ? 1.000 ? xwe hold time t weh 0.000 ? 0.000 ? 0.000 ? 0.000 ? xwa setup time t was 1.000 ? 1.000 ? 1.000 ? 1.000 ? xwa hold time t wah 0.000 ? 0.000 ? 0.000 ? 0.000 ? address hold time t ah 0.000 ? 0.000 ? 0.000 ? 0.000 ? data hold time t dh 0.000 ? 0.000 ? 0.000 ? 0.000 ? data setup time t ds 1.000 ? 1.000 ? 1.000 ? 1.000 ? write data hold time t wdh 1.437 ? 1.474 ? 1.528 ? 1.536 ? write data through time t wdt ? 3.486 ? 3.601 ? 3.698 ? 3.801 ns chapter 6 memory blocks embedded array S1X60000 series epson 129 design guide (5) 2.5 v specifications (v dd = 2.3 to 2.7 v, t a = -40 to +85c) 192 words 1 port/2 port ram read cycle ac characteristics table sj0c008/ sk0c008 sj0c010/ sk0c010 sj0c018/ sk0c018 sj0c020/ sk0c020 parameter symbol min. max. min. max. min. max. min. max. unit access time t acs , t acc ? 6.076 ? 6.133 ? 6.198 ? 6.268 read cycle time t rcy 6.076 ? 6.133 ? 6.198 ? 6.268 ? clock high pulse width t ckh 0.500 ? 0.500 ? 0.500 ? 0.500 ? clock low pulse width t ckl 0.500 ? 0.500 ? 0.500 ? 0.500 ? xcs setup time t css 1.000 ? 1.000 ? 1.000 ? 1.000 ? xcs hold time t csh 0.000 ? 0.000 ? 0.000 ? 0.000 ? xwe setup time t wes 1.000 ? 1.000 ? 1.000 ? 1.000 ? xwe hold time t weh 0.000 ? 0.000 ? 0.000 ? 0.000 ? xrb setup time t rbs 1.000 ? 1.000 ? 1.000 ? 1.000 ? xrb hold time t rbh 0.000 ? 0.000 ? 0.000 ? 0.000 ? address setup time t as 1.000 ? 1.000 ? 1.000 ? 1.000 ? address hold time t ah 0.000 ? 0.000 ? 0.000 ? 0.000 ? output hold time t oh 0.652 ? 0.671 ? 0.690 ? 0.705 ? ns 1 port/2 port ram write cycle ac characteristics table sj0c008/ sk0c008 sj0c010/ sk0c010 sj0c018/ sk0c018 sj0c020/ sk0c020 parameter symbol min. max. min. max. min. max. min. max. unit write cycle time t wcy 3.748 ? 3.857 ? 3.970 ? 4.077 ? clock high pulse width t ckh 0.500 ? 0.500 ? 0.500 ? 0.500 ? clock low pulse width t ckl 0.500 ? 0.500 ? 0.500 ? 0.500 ? xcs setup time t css 1.000 ? 1.000 ? 1.000 ? 1.000 ? xcs hold time t csh 0.000 ? 0.000 ? 0.000 ? 0.000 ? address setup time t as 1.000 ? 1.000 ? 1.000 ? 1.000 ? xwe setup time t wes 1.000 ? 1.000 ? 1.000 ? 1.000 ? xwe hold time t weh 0.000 ? 0.000 ? 0.000 ? 0.000 ? xwa setup time t was 1.000 ? 1.000 ? 1.000 ? 1.000 ? xwa hold time t wah 0.000 ? 0.000 ? 0.000 ? 0.000 ? address hold time t ah 0.000 ? 0.000 ? 0.000 ? 0.000 ? data hold time t dh 0.000 ? 0.000 ? 0.000 ? 0.000 ? data setup time t ds 1.000 ? 1.000 ? 1.000 ? 1.000 ? write data hold time t wdh 1.372 ? 1.407 ? 1.440 ? 1.467 ? write data through time t wdt ? 3.748 ? 3.857 ? 3.970 ? 4.077 ns chapter 6 memory blocks 130 epson embedded array S1X60000 series design guide (6) 2.5 v specifications (v dd = 2.3 to 2.7 v, t a = 0 to +70c) 192 words 1 port/2 port ram read cycle ac characteristics table sj0c008/ sk0c008 sj0c010/ sk0c010 sj0c018/ sk0c018 sj0c020/ sk0c020 parameter symbol min. max. min. max. min. max. min. max. unit access time t acs , t acc ? 5.748 ? 5.802 ? 5.863 ? 5.929 read cycle time t rcy 5.748 ? 5.802 ? 5.863 ? 5.929 ? clock high pulse width t ckh 0.500 ? 0.500 ? 0.500 ? 0.500 ? clock low pulse width t ckl 0.500 ? 0.500 ? 0.500 ? 0.500 ? xcs setup time t css 1.000 ? 1.000 ? 1.000 ? 1.000 ? xcs hold time t csh 0.000 ? 0.000 ? 0.000 ? 0.000 ? xwe setup time t wes 1.000 ? 1.000 ? 1.000 ? 1.000 ? xwe hold time t weh 0.000 ? 0.000 ? 0.000 ? 0.000 ? xrb setup time t rbs 1.000 ? 1.000 ? 1.000 ? 1.000 ? xrb hold time t rbh 0.000 ? 0.000 ? 0.000 ? 0.000 ? address setup time t as 1.000 ? 1.000 ? 1.000 ? 1.000 ? address hold time t ah 0.000 ? 0.000 ? 0.000 ? 0.000 ? output hold time t oh 0.698 ? 0.719 ? 0.739 ? 0.756 ? ns 1 port/2 port ram write cycle ac characteristics table sj0c008/ sk0c008 sj0c010/ sk0c010 sj0c018/ sk0c018 sj0c020/ sk0c020 parameter symbol min. max. min. max. min. max. min. max. unit write cycle time t wcy 3.546 ? 3.649 ? 3.755 ? 3.857 ? clock high pulse width t ckh 0.500 ? 0.500 ? 0.500 ? 0.500 ? clock low pulse width t ckl 0.500 ? 0.500 ? 0.500 ? 0.500 ? xcs setup time t css 1.000 ? 1.000 ? 1.000 ? 1.000 ? xcs hold time t csh 0.000 ? 0.000 ? 0.000 ? 0.000 ? address setup time t as 1.000 ? 1.000 ? 1.000 ? 1.000 ? xwe setup time t wes 1.000 ? 1.000 ? 1.000 ? 1.000 ? xwe hold time t weh 0.000 ? 0.000 ? 0.000 ? 0.000 ? xwa setup time t was 1.000 ? 1.000 ? 1.000 ? 1.000 ? xwa hold time t wah 0.000 ? 0.000 ? 0.000 ? 0.000 ? address hold time t ah 0.000 ? 0.000 ? 0.000 ? 0.000 ? data hold time t dh 0.000 ? 0.000 ? 0.000 ? 0.000 ? data setup time t ds 1.000 ? 1.000 ? 1.000 ? 1.000 ? write data hold time t wdh 1.470 ? 1.507 ? 1.543 ? 1.572 ? write data through time t wdt ? 3.546 ? 3.649 ? 3.755 ? 3.857 ns chapter 6 memory blocks embedded array S1X60000 series epson 131 design guide (7) 2.5 v specifications (v dd = 2.3 to 2.7 v, t a = -40 to +85c) 256 words 1 port/2 port ram read cycle ac characteristics table sj10008/ sk10008 sj10010/ sk10010 sj10018/ sk10018 sj10020/ sk10020 parameter symbol min. max. min. max. min. max. min. max. unit access time t acs , t acc ? 7.004 ? 7.073 ? 7.138 ? 7.208 read cycle time t rcy 7.004 ? 7.073 ? 7.138 ? 7.208 ? clock high pulse width t ckh 0.500 ? 0.500 ? 0.500 ? 0.500 ? clock low pulse width t ckl 0.500 ? 0.500 ? 0.500 ? 0.500 ? xcs setup time t css 1.000 ? 1.000 ? 1.000 ? 1.000 ? xcs hold time t csh 0.000 ? 0.000 ? 0.000 ? 0.000 ? xwe setup time t wes 1.000 ? 1.000 ? 1.000 ? 1.000 ? xwe hold time t weh 0.000 ? 0.000 ? 0.000 ? 0.000 ? xrb setup time t rbs 1.000 ? 1.000 ? 1.000 ? 1.000 ? xrb hold time t rbh 0.000 ? 0.000 ? 0.000 ? 0.000 ? address setup time t as 1.000 ? 1.000 ? 1.000 ? 1.000 ? address hold time t ah 0.000 ? 0.000 ? 0.000 ? 0.000 ? output hold time t oh 0.652 ? 0.672 ? 0.690 ? 0.705 ? ns 1 port/2 port ram write cycle ac characteristics table sj10008/ sk10008 sj10010/ sk10010 sj10018/ sk10018 sj10020/ sk10020 parameter symbol min. max. min. max. min. max. min. max. unit write cycle time t wcy 3.794 ? 3.901 ? 4.004 ? 4.118 ? clock high pulse width t ckh 0.500 ? 0.500 ? 0.500 ? 0.500 ? clock low pulse width t ckl 0.500 ? 0.500 ? 0.500 ? 0.500 ? xcs setup time t css 1.000 ? 1.000 ? 1.000 ? 1.000 ? xcs hold time t csh 0.000 ? 0.000 ? 0.000 ? 0.000 ? address setup time t as 1.000 ? 1.000 ? 1.000 ? 1.000 ? xwe setup time t wes 1.000 ? 1.000 ? 1.000 ? 1.000 ? xwe hold time t weh 0.000 ? 0.000 ? 0.000 ? 0.000 ? xwa setup time t was 1.000 ? 1.000 ? 1.000 ? 1.000 ? xwa hold time t wah 0.000 ? 0.000 ? 0.000 ? 0.000 ? address hold time t ah 0.000 ? 0.000 ? 0.000 ? 0.000 ? data hold time t dh 0.000 ? 0.000 ? 0.000 ? 0.000 ? data setup time t ds 1.000 ? 1.000 ? 1.000 ? 1.000 ? write data hold time t wdh 1.398 ? 1.431 ? 1.464 ? 1.491 ? write data through time t wdt ? 3.794 ? 3.901 ? 4.004 ? 4.118 ns chapter 6 memory blocks 132 epson embedded array S1X60000 series design guide (8) 2.5 v specifications (v dd = 2.3 to 2.7 v, t a = 0 to +70c) 256 words 1 port/2 port ram read cycle ac characteristics table sj10008/ sk10008 sj10010/ sk10010 sj10018/ sk10018 sj10020/ sk10020 parameter symbol min. max. min. max. min. max. min. max. unit access time t acs , t acc ? 6.626 ? 6.690 ? 6.752 ? 6.818 read cycle time t rcy 6.626 ? 6.690 ? 6.752 ? 6.818 ? clock high pulse width t ckh 0.500 ? 0.500 ? 0.500 ? 0.500 ? clock low pulse width t ckl 0.500 ? 0.500 ? 0.500 ? 0.500 ? xcs setup time t css 1.000 ? 1.000 ? 1.000 ? 1.000 ? xcs hold time t csh 0.000 ? 0.000 ? 0.000 ? 0.000 ? xwe setup time t wes 1.000 ? 1.000 ? 1.000 ? 1.000 ? xwe hold time t weh 0.000 ? 0.000 ? 0.000 ? 0.000 ? xrb setup time t rbs 1.000 ? 1.000 ? 1.000 ? 1.000 ? xrb hold time t rbh 0.000 ? 0.000 ? 0.000 ? 0.000 ? address setup time t as 1.000 ? 1.000 ? 1.000 ? 1.000 ? address hold time t ah 0.000 ? 0.000 ? 0.000 ? 0.000 ? output hold time t oh 0.698 ? 0.720 ? 0.739 ? 0.756 ? ns 1 port/2 port ram write cycle ac characteristics table sj10008/ sk10008 sj10010/ sk10010 sj10018/ sk10018 sj10020/ sk10020 parameter symbol min. max. min. max. min. max. min. max. unit write cycle time t wcy 3.589 ? 3.690 ? 3.787 ? 3.895 ? clock high pulse width t ckh 0.500 ? 0.500 ? 0.500 ? 0.500 ? clock low pulse width t ckl 0.500 ? 0.500 ? 0.500 ? 0.500 ? xcs setup time t css 1.000 ? 1.000 ? 1.000 ? 1.000 ? xcs hold time t csh 0.000 ? 0.000 ? 0.000 ? 0.000 ? address setup time t as 1.000 ? 1.000 ? 1.000 ? 1.000 ? xwe setup time t wes 1.000 ? 1.000 ? 1.000 ? 1.000 ? xwe hold time t weh 0.000 ? 0.000 ? 0.000 ? 0.000 ? xwa setup time t was 1.000 ? 1.000 ? 1.000 ? 1.000 ? xwa hold time t wah 0.000 ? 0.000 ? 0.000 ? 0.000 ? address hold time t ah 0.000 ? 0.000 ? 0.000 ? 0.000 ? data hold time t dh 0.000 ? 0.000 ? 0.000 ? 0.000 ? data setup time t ds 1.000 ? 1.000 ? 1.000 ? 1.000 ? write data hold time t wdh 1.498 ? 1.534 ? 1.568 ? 1.598 ? write data through time t wdt ? 3.589 ? 3.690 ? 3.787 ? 3.895 ns chapter 6 memory blocks embedded array S1X60000 series epson 133 design guide (9) 2.0 v specifications (v dd = 1.8 to 2.2 v, t a = -40 to +85c) 64 words 1 port/2 port ram read cycle ac characteristics table sj04008/ sk04008 sj04010/ sk04010 sj04018/ sk04018 sj04020/ sk04020 parameter symbol min. max. min. max. min. max. min. max. unit access time t acs , t acc ? 5.630 ? 5.725 ? 5.848 ? 5.966 read cycle time t rcy 5.630 ? 5.725 ? 5.848 ? 5.966 ? clock high pulse width t ckh 0.500 ? 0.500 ? 0.500 ? 0.500 ? clock low pulse width t ckl 0.500 ? 0.500 ? 0.500 ? 0.500 ? xcs setup time t css 1.500 ? 1.500 ? 1.500 ? 1.500 ? xcs hold time t csh 0.000 ? 0.000 ? 0.000 ? 0.000 ? xwe setup time t wes 1.500 ? 1.500 ? 1.500 ? 1.500 ? xwe hold time t weh 0.000 ? 0.000 ? 0.000 ? 0.000 ? xrb setup time t rbs 1.500 ? 1.500 ? 1.500 ? 1.500 ? xrb hold time t rbh 0.000 ? 0.000 ? 0.000 ? 0.000 ? address setup time t as 1.500 ? 1.500 ? 1.500 ? 1.500 ? address hold time t ah 0.000 ? 0.000 ? 0.000 ? 0.000 ? output hold time t oh 0.758 ? 0.789 ? 0.808 ? 0.825 ? ns 1 port/2 port ram write cycle ac characteristics table sj04008/ sk04008 sj04010/ sk04010 sj04018/ sk04018 sj04020/ sk04020 parameter symbol min. max. min. max. min. max. min. max. unit write cycle time t wcy 5.125 ? 5.282 ? 5.445 ? 5.607 ? clock high pulse width t ckh 0.500 ? 0.500 ? 0.500 ? 0.500 ? clock low pulse width t ckl 0.500 ? 0.500 ? 0.500 ? 0.500 ? xcs setup time t css 1.500 ? 1.500 ? 1.500 ? 1.500 ? xcs hold time t csh 0.000 ? 0.000 ? 0.000 ? 0.000 ? address setup time t as 1.500 ? 1.500 ? 1.500 ? 1.500 ? xwe setup time t wes 1.500 ? 1.500 ? 1.500 ? 1.500 ? xwe hold time t weh 0.000 ? 0.000 ? 0.000 ? 0.000 ? xwa setup time t was 1.500 ? 1.500 ? 1.500 ? 1.500 ? xwa hold time t wah 0.000 ? 0.000 ? 0.000 ? 0.000 ? address hold time t ah 0.000 ? 0.000 ? 0.000 ? 0.000 ? data hold time t dh 0.000 ? 0.000 ? 0.000 ? 0.000 ? data setup time t ds 1.500 ? 1.500 ? 1.500 ? 1.500 ? write data hold time t wdh 1.577 ? 1.624 ? 1.660 ? 1.697 ? write data through time t wdt ? 5.125 ? 5.282 ? 5.445 ? 5.607 ns chapter 6 memory blocks 134 epson embedded array S1X60000 series design guide (10) 2.0 v specifications (v dd = 1.8 to 2.2 v, t a = 0 to +70c) 64 words 1 port/2 port ram read cycle ac characteristics table sj04008/ sk04008 sj04010/ sk04010 sj04018/ sk04018 sj04020/ sk04020 parameter symbol min. max. min. max. min. max. min. max. unit access time t acs , t acc ? 5.341 ? 5.431 ? 5.548 ? 5.660 read cycle time t rcy 5.341 ? 5.431 ? 5.548 ? 5.660 ? clock high pulse width t ckh 0.500 ? 0.500 ? 0.500 ? 0.500 ? clock low pulse width t ckl 0.500 ? 0.500 ? 0.500 ? 0.500 ? xcs setup time t css 1.500 ? 1.500 ? 1.500 ? 1.500 ? xcs hold time t csh 0.000 ? 0.000 ? 0.000 ? 0.000 ? xwe setup time t wes 1.500 ? 1.500 ? 1.500 ? 1.500 ? xwe hold time t weh 0.000 ? 0.000 ? 0.000 ? 0.000 ? xrb setup time t rbs 1.500 ? 1.500 ? 1.500 ? 1.500 ? xrb hold time t rbh 0.000 ? 0.000 ? 0.000 ? 0.000 ? address setup time t as 1.500 ? 1.500 ? 1.500 ? 1.500 ? address hold time t ah 0.000 ? 0.000 ? 0.000 ? 0.000 ? output hold time t oh 0.802 ? 0.836 ? 0.856 ? 0.874 ? ns 1 port/2 port ram write cycle ac characteristics table sj04008/ sk04008 sj04010/ sk04010 sj04018/ sk04018 sj04020/ sk04020 parameter symbol min. max. min. max. min. max. min. max. unit write cycle time t wcy 4.862 ? 5.011 ? 5.165 ? 5.319 ? clock high pulse width t ckh 0.500 ? 0.500 ? 0.500 ? 0.500 ? clock low pulse width t ckl 0.500 ? 0.500 ? 0.500 ? 0.500 ? xcs setup time t css 1.500 ? 1.500 ? 1.500 ? 1.500 ? xcs hold time t csh 0.000 ? 0.000 ? 0.000 ? 0.000 ? address setup time t as 1.500 ? 1.500 ? 1.500 ? 1.500 ? xwe setup time t wes 1.500 ? 1.500 ? 1.500 ? 1.500 ? xwe hold time t weh 0.000 ? 0.000 ? 0.000 ? 0.000 ? xwa setup time t was 1.500 ? 1.500 ? 1.500 ? 1.500 ? xwa hold time t wah 0.000 ? 0.000 ? 0.000 ? 0.000 ? address hold time t ah 0.000 ? 0.000 ? 0.000 ? 0.000 ? data hold time t dh 0.000 ? 0.000 ? 0.000 ? 0.000 ? data setup time t ds 1.500 ? 1.500 ? 1.500 ? 1.500 ? write data hold time t wdh 1.670 ? 1.720 ? 1.758 ? 1.797 ? write data through time t wdt ? 4.862 ? 5.011 ? 5.165 ? 5.319 ns chapter 6 memory blocks embedded array S1X60000 series epson 135 design guide (11) 2.0 v specifications (v dd = 1.8 to 2.2 v, t a = -40 to +85c) 128 words 1 port/2 port ram read cycle ac characteristics table sj08008/ sk08008 sj08010/ sk08010 sj08018/ sk08018 sj08020/ sk08020 parameter symbol min. max. min. max. min. max. min. max. unit access time t acs , t acc ? 7.108 ? 7.200 ? 7.302 ? 7.458 read cycle time t rcy 7.108 ? 7.200 ? 7.302 ? 7.458 ? clock high pulse width t ckh 0.500 ? 0.500 ? 0.500 ? 0.500 ? clock low pulse width t ckl 0.500 ? 0.500 ? 0.500 ? 0.500 ? xcs setup time t css 1.500 ? 1.500 ? 1.500 ? 1.500 ? xcs hold time t csh 0.000 ? 0.000 ? 0.000 ? 0.000 ? xwe setup time t wes 1.500 ? 1.500 ? 1.500 ? 1.500 ? xwe hold time t weh 0.000 ? 0.000 ? 0.000 ? 0.000 ? xrb setup time t rbs 1.500 ? 1.500 ? 1.500 ? 1.500 ? xrb hold time t rbh 0.000 ? 0.000 ? 0.000 ? 0.000 ? address setup time t as 1.500 ? 1.500 ? 1.500 ? 1.500 ? address hold time t ah 0.000 ? 0.000 ? 0.000 ? 0.000 ? output hold time t oh 0.778 ? 0.800 ? 0.820 ? 0.841 ? ns 1 port/2 port ram write cycle ac characteristics table sj08008/ sk08008 sj08010/ sk08010 sj08018/ sk08018 sj08020/ sk08020 parameter symbol min. max. min. max. min. max. min. max. unit write cycle time t wcy 5.243 ? 5.417 ? 5.563 ? 5.718 ? clock high pulse width t ckh 0.500 ? 0.500 ? 0.500 ? 0.500 ? clock low pulse width t ckl 0.500 ? 0.500 ? 0.500 ? 0.500 ? xcs setup time t css 1.500 ? 1.500 ? 1.500 ? 1.500 ? xcs hold time t csh 0.000 ? 0.000 ? 0.000 ? 0.000 ? address setup time t as 1.500 ? 1.500 ? 1.500 ? 1.500 ? xwe setup time t wes 1.500 ? 1.500 ? 1.500 ? 1.500 ? xwe hold time t weh 0.000 ? 0.000 ? 0.000 ? 0.000 ? xwa setup time t was 1.500 ? 1.500 ? 1.500 ? 1.500 ? xwa hold time t wah 0.000 ? 0.000 ? 0.000 ? 0.000 ? address hold time t ah 0.000 ? 0.000 ? 0.000 ? 0.000 ? data hold time t dh 0.000 ? 0.000 ? 0.000 ? 0.000 ? data setup time t ds 1.500 ? 1.500 ? 1.500 ? 1.500 ? write data hold time t wdh 1.629 ? 1.671 ? 1.732 ? 1.741 ? write data through time t wdt ? 5.243 ? 5.417 ? 5.563 ? 5.718 ns chapter 6 memory blocks 136 epson embedded array S1X60000 series design guide (12) 2.0 v specifications (v dd = 1.8 to 2.2 v, t a = 0 to +70c) 128 words 1 port/2 port ram read cycle ac characteristics table sj08008/ sk08008 sj08010/ sk08010 sj08018/ sk08018 sj08020/ sk08020 parameter symbol min. max. min. max. min. max. min. max. unit access time t acs , t acc ? 6.743 ? 6.831 ? 6.928 ? 7.075 read cycle time t rcy 6.743 ? 6.831 ? 6.928 ? 7.075 ? clock high pulse width t ckh 0.500 ? 0.500 ? 0.500 ? 0.500 ? clock low pulse width t ckl 0.500 ? 0.500 ? 0.500 ? 0.500 ? xcs setup time t css 1.500 ? 1.500 ? 1.500 ? 1.500 ? xcs hold time t csh 0.000 ? 0.000 ? 0.000 ? 0.000 ? xwe setup time t wes 1.500 ? 1.500 ? 1.500 ? 1.500 ? xwe hold time t weh 0.000 ? 0.000 ? 0.000 ? 0.000 ? xrb setup time t rbs 1.500 ? 1.500 ? 1.500 ? 1.500 ? xrb hold time t rbh 0.000 ? 0.000 ? 0.000 ? 0.000 ? address setup time t as 1.500 ? 1.500 ? 1.500 ? 1.500 ? address hold time t ah 0.000 ? 0.000 ? 0.000 ? 0.000 ? output hold time t oh 0.823 ? 0.847 ? 0.868 ? 0.891 ? ns 1 port/2 port ram write cycle ac characteristics table sj08008/ sk08008 sj08010/ sk08010 sj08018/ sk08018 sj08020/ sk08020 parameter symbol min. max. min. max. min. max. min. max. unit write cycle time t wcy 4.974 ? 5.139 ? 5.277 ? 5.425 ? clock high pulse width t ckh 0.500 ? 0.500 ? 0.500 ? 0.500 ? clock low pulse width t ckl 0.500 ? 0.500 ? 0.500 ? 0.500 ? xcs setup time t css 1.500 ? 1.500 ? 1.500 ? 1.500 ? xcs hold time t csh 0.000 ? 0.000 ? 0.000 ? 0.000 ? address setup time t as 1.500 ? 1.500 ? 1.500 ? 1.500 ? xwe setup time t wes 1.500 ? 1.500 ? 1.500 ? 1.500 ? xwe hold time t weh 0.000 ? 0.000 ? 0.000 ? 0.000 ? xwa setup time t was 1.500 ? 1.500 ? 1.500 ? 1.500 ? xwa hold time t wah 0.000 ? 0.000 ? 0.000 ? 0.000 ? address hold time t ah 0.000 ? 0.000 ? 0.000 ? 0.000 ? data hold time t dh 0.000 ? 0.000 ? 0.000 ? 0.000 ? data setup time t ds 1.500 ? 1.500 ? 1.500 ? 1.500 ? write data hold time t wdh 1.725 ? 1.769 ? 1.834 ? 1.843 ? write data through time t wdt ? 4.974 ? 5.139 ? 5.277 ? 5.425 ns chapter 6 memory blocks embedded array S1X60000 series epson 137 design guide (13) 2.0 v specifications (v dd = 1.8 to 2.2 v, t a = -40 to +85c) 192 words 1 port/2 port ram read cycle ac characteristics table sj0c008/ sk0c008 sj0c010/ sk0c010 sj0c018/ sk0c018 sj0c020/ sk0c020 parameter symbol min. max. min. max. min. max. min. max. unit access time t acs , t acc ? 8.646 ? 8.727 ? 8.820 ? 8.919 read cycle time t rcy 8.646 ? 8.727 ? 8.820 ? 8.919 ? clock high pulse width t ckh 0.500 ? 0.500 ? 0.500 ? 0.500 ? clock low pulse width t ckl 0.500 ? 0.500 ? 0.500 ? 0.500 ? xcs setup time t css 1.500 ? 1.500 ? 1.500 ? 1.500 ? xcs hold time t csh 0.000 ? 0.000 ? 0.000 ? 0.000 ? xwe setup time t wes 1.500 ? 1.500 ? 1.500 ? 1.500 ? xwe hold time t weh 0.000 ? 0.000 ? 0.000 ? 0.000 ? xrb setup time t rbs 1.500 ? 1.500 ? 1.500 ? 1.500 ? xrb hold time t rbh 0.000 ? 0.000 ? 0.000 ? 0.000 ? address setup time t as 1.500 ? 1.500 ? 1.500 ? 1.500 ? address hold time t ah 0.000 ? 0.000 ? 0.000 ? 0.000 ? output hold time t oh 0.792 ? 0.815 ? 0.837 ? 0.857 ? ns 1 port/2 port ram write cycle ac characteristics table sj0c008/ sk0c008 sj0c010/ sk0c010 sj0c018/ sk0c018 sj0c020/ sk0c020 parameter symbol min. max. min. max. min. max. min. max. unit write cycle time t wcy 5.333 ? 5.489 ? 5.648 ? 5.801 ? clock high pulse width t ckh 0.500 ? 0.500 ? 0.500 ? 0.500 ? clock low pulse width t ckl 0.500 ? 0.500 ? 0.500 ? 0.500 ? xcs setup time t css 1.500 ? 1.500 ? 1.500 ? 1.500 ? xcs hold time t csh 0.000 ? 0.000 ? 0.000 ? 0.000 ? address setup time t as 1.500 ? 1.500 ? 1.500 ? 1.500 ? xwe setup time t wes 1.500 ? 1.500 ? 1.500 ? 1.500 ? xwe hold time t weh 0.000 ? 0.000 ? 0.000 ? 0.000 ? xwa setup time t was 1.500 ? 1.500 ? 1.500 ? 1.500 ? xwa hold time t wah 0.000 ? 0.000 ? 0.000 ? 0.000 ? address hold time t ah 0.000 ? 0.000 ? 0.000 ? 0.000 ? data hold time t dh 0.000 ? 0.000 ? 0.000 ? 0.000 ? data setup time t ds 1.500 ? 1.500 ? 1.500 ? 1.500 ? write data hold time t wdh 1.666 ? 1.709 ? 1.748 ? 1.782 ? write data through time t wdt ? 5.333 ? 5.489 ? 5.648 ? 5.801 ns chapter 6 memory blocks 138 epson embedded array S1X60000 series design guide (14) 2.0 v specifications (v dd = 1.8 to 2.2 v, t a = 0 to +70c) 192 words 1 port/2 port ram read cycle ac characteristics table sj0c008/ sk0c008 sj0c010/ sk0c010 sj0c018/ sk0c018 sj0c020/ sk0c020 parameter symbol min. max. min. max. min. max. min. max. unit access time t acs , t acc ? 8.203 ? 8.280 ? 8.368 ? 8.462 read cycle time t rcy 8.203 ? 8.280 ? 8.368 ? 8.462 ? clock high pulse width t ckh 0.500 ? 0.500 ? 0.500 ? 0.500 ? clock low pulse width t ckl 0.500 ? 0.500 ? 0.500 ? 0.500 ? xcs setup time t css 1.500 ? 1.500 ? 1.500 ? 1.500 ? xcs hold time t csh 0.000 ? 0.000 ? 0.000 ? 0.000 ? xwe setup time t wes 1.500 ? 1.500 ? 1.500 ? 1.500 ? xwe hold time t weh 0.000 ? 0.000 ? 0.000 ? 0.000 ? xrb setup time t rbs 1.500 ? 1.500 ? 1.500 ? 1.500 ? xrb hold time t rbh 0.000 ? 0.000 ? 0.000 ? 0.000 ? address setup time t as 1.500 ? 1.500 ? 1.500 ? 1.500 ? address hold time t ah 0.000 ? 0.000 ? 0.000 ? 0.000 ? output hold time t oh 0.838 ? 0.863 ? 0.887 ? 0.907 ? ns 1 port/2 port ram write cycle ac characteristics table sj0c008/ sk0c008 sj0c010/ sk0c010 sj0c018/ sk0c018 sj0c020/ sk0c020 parameter symbol min. max. min. max. min. max. min. max. unit write cycle time t wcy 5.060 ? 5.207 ? 5.359 ? 5.504 ? clock high pulse width t ckh 0.500 ? 0.500 ? 0.500 ? 0.500 ? clock low pulse width t ckl 0.500 ? 0.500 ? 0.500 ? 0.500 ? xcs setup time t css 1.500 ? 1.500 ? 1.500 ? 1.500 ? xcs hold time t csh 0.000 ? 0.000 ? 0.000 ? 0.000 ? address setup time t as 1.500 ? 1.500 ? 1.500 ? 1.500 ? xwe setup time t wes 1.500 ? 1.500 ? 1.500 ? 1.500 ? xwe hold time t weh 0.000 ? 0.000 ? 0.000 ? 0.000 ? xwa setup time t was 1.500 ? 1.500 ? 1.500 ? 1.500 ? xwa hold time t wah 0.000 ? 0.000 ? 0.000 ? 0.000 ? address hold time t ah 0.000 ? 0.000 ? 0.000 ? 0.000 ? data hold time t dh 0.000 ? 0.000 ? 0.000 ? 0.000 ? data setup time t ds 1.500 ? 1.500 ? 1.500 ? 1.500 ? write data hold time t wdh 1.764 ? 1.809 ? 1.851 ? 1.887 ? write data through time t wdt ? 5.060 ? 5.207 ? 5.359 ? 5.504 ns chapter 6 memory blocks embedded array S1X60000 series epson 139 design guide (15) 2.0 v specifications (v dd = 1.8 to 2.2 v, t a = -40 to +85c) 256 words 1 port/2 port ram read cycle ac characteristics table sj10008/ sk10008 sj10010/ sk10010 sj10018/ sk10018 sj10020/ sk10020 parameter symbol min. max. min. max. min. max. min. max. unit access time t acs , t acc ? 9.967 ? 10.064 ? 10.156 ? 10.256 read cycle time t rcy 9.967 ? 10.064 ? 10.156 ? 10.256 ? clock high pulse width t ckh 0.500 ? 0.500 ? 0.500 ? 0.500 ? clock low pulse width t ckl 0.500 ? 0.500 ? 0.500 ? 0.500 ? xcs setup time t css 1.500 ? 1.500 ? 1.500 ? 1.500 ? xcs hold time t csh 0.000 ? 0.000 ? 0.000 ? 0.000 ? xwe setup time t wes 1.500 ? 1.500 ? 1.500 ? 1.500 ? xwe hold time t weh 0.000 ? 0.000 ? 0.000 ? 0.000 ? xrb setup time t rbs 1.500 ? 1.500 ? 1.500 ? 1.500 ? xrb hold time t rbh 0.000 ? 0.000 ? 0.000 ? 0.000 ? address setup time t as 1.500 ? 1.500 ? 1.500 ? 1.500 ? address hold time t ah 0.000 ? 0.000 ? 0.000 ? 0.000 ? output hold time t oh 0.792 ? 0.815 ? 0.837 ? 0.857 ? ns 1 port/2 port ram write cycle ac characteristics table sj10008/ sk10008 sj10010/ sk10010 sj10018/ sk10018 sj10020/ sk10020 parameter symbol min. max. min. max. min. max. min. max. unit write cycle time t wcy 5.398 ? 5.551 ? 5.697 ? 5.859 ? clock high pulse width t ckh 0.500 ? 0.500 ? 0.500 ? 0.500 ? clock low pulse width t ckl 0.500 ? 0.500 ? 0.500 ? 0.500 ? xcs setup time t css 1.500 ? 1.500 ? 1.500 ? 1.500 ? xcs hold time t csh 0.000 ? 0.000 ? 0.000 ? 0.000 ? address setup time t as 1.500 ? 1.500 ? 1.500 ? 1.500 ? xwe setup time t wes 1.500 ? 1.500 ? 1.500 ? 1.500 ? xwe hold time t weh 0.000 ? 0.000 ? 0.000 ? 0.000 ? xwa setup time t was 1.500 ? 1.500 ? 1.500 ? 1.500 ? xwa hold time t wah 0.000 ? 0.000 ? 0.000 ? 0.000 ? address hold time t ah 0.000 ? 0.000 ? 0.000 ? 0.000 ? data hold time t dh 0.000 ? 0.000 ? 0.000 ? 0.000 ? data setup time t ds 1.500 ? 1.500 ? 1.500 ? 1.500 ? write data hold time t wdh 1.698 ? 1.738 ? 1.777 ? 1.811 ? write data through time t wdt ? 5.398 ? 5.551 ? 5.697 ? 5.859 ns chapter 6 memory blocks 140 epson embedded array S1X60000 series design guide (16) 2.0 v specifications (v dd = 1.8 to 2.2 v, t a = 0 to +70c) 256 words 1 port/2 port ram read cycle ac characteristics table sj10008/ sk10008 sj10010/ sk10010 sj10018/ sk10018 sj10020/ sk10020 parameter symbol min. max. min. max. min. max. min. max. unit access time t acs , t acc ? 9.455 ? 9.548 ? 9.636 ? 9.730 read cycle time t rcy 9.455 ? 9.548 ? 9.636 ? 9.730 ? clock high pulse width t ckh 0.500 ? 0.500 ? 0.500 ? 0.500 ? clock low pulse width t ckl 0.500 ? 0.500 ? 0.500 ? 0.500 ? xcs setup time t css 1.500 ? 1.500 ? 1.500 ? 1.500 ? xcs hold time t csh 0.000 ? 0.000 ? 0.000 ? 0.000 ? xwe setup time t wes 1.500 ? 1.500 ? 1.500 ? 1.500 ? xwe hold time t weh 0.000 ? 0.000 ? 0.000 ? 0.000 ? xrb setup time t rbs 1.500 ? 1.500 ? 1.500 ? 1.500 ? xrb hold time t rbh 0.000 ? 0.000 ? 0.000 ? 0.000 ? address setup time t as 1.500 ? 1.500 ? 1.500 ? 1.500 ? address hold time t ah 0.000 ? 0.000 ? 0.000 ? 0.000 ? output hold time t oh 0.873 ? 0.899 ? 0.924 ? 0.945 ? ns 1 port/2 port ram write cycle ac characteristics table sj10008/ sk10008 sj10010/ sk10010 sj10018/ sk10018 sj10020/ sk10020 parameter symbol min. max. min. max. min. max. min. max. unit write cycle time t wcy 5.121 ? 5.266 ? 5.405 ? 5.559 ? clock high pulse width t ckh 0.500 ? 0.500 ? 0.500 ? 0.500 ? clock low pulse width t ckl 0.500 ? 0.500 ? 0.500 ? 0.500 ? xcs setup time t css 1.500 ? 1.500 ? 1.500 ? 1.500 ? xcs hold time t csh 0.000 ? 0.000 ? 0.000 ? 0.000 ? address setup time t as 1.500 ? 1.500 ? 1.500 ? 1.500 ? xwe setup time t wes 1.500 ? 1.500 ? 1.500 ? 1.500 ? xwe hold time t weh 0.000 ? 0.000 ? 0.000 ? 0.000 ? xwa setup time t was 1.500 ? 1.500 ? 1.500 ? 1.500 ? xwa hold time t wah 0.000 ? 0.000 ? 0.000 ? 0.000 ? address hold time t ah 0.000 ? 0.000 ? 0.000 ? 0.000 ? data hold time t dh 0.000 ? 0.000 ? 0.000 ? 0.000 ? data setup time t ds 1.500 ? 1.500 ? 1.500 ? 1.500 ? write data hold time t wdh 1.798 ? 1.841 ? 1.882 ? 1.918 ? write data through time t wdt ? 5.121 ? 5.266 ? 5.405 ? 5.559 ns chapter 6 memory blocks embedded array S1X60000 series epson 141 design guide 6.3 standard type 1 port ram 6.3.1 features ? for this type of ram, the circuit and layout pattern are exclusively designed as 1 port ram in order to reduce the area that the ram occupies. (three al layers are used.) ? can be configured in a wide range of memory capacities (128 to 64k bits), and provides superior flexibility for selection of the height to width ratio of the layout shape. furthermore, if large capacity memory is required, multiple pieces of memory macros may be used. ? can be accessed at high speed and consumes less current than other rams of the same class. ? the chip select, write enable, byte write enable, address, and data input/output parts contain a latch circuit, making the ram capable of clock synchronized, high speed operation. ? the data input port and data output port are separate. ? a byte write function is included, allowing the bits of write data to be selected in byte units. ? the data output part contains a latch circuit, so that readout data is output continuously until the next read cycle. 6.3.2 ram sizes the sizes of standard type 1 port rams vary in a complicated manner depending on the word/bit configurations. for detailed information on ram sizes, please contact the sales division of epson. chapter 6 memory blocks 142 epson embedded array S1X60000 series design guide 6.3.3 input signals and block diagrams input/output signal symbol name description ck clock input chip select (xcs), write enable (xwe), byte write enable (xbwen), address input (a0 to an), and data input (d0 to dn) are latched into the rising edge (low to high transition) of the clock input (ck). memory is activated when the latched chip select signal is low. while memory is active, data is written to memory when the latched write enable signal is low, or read from memory when the signal is high. operation finishes on the next fall of the clock. xcs chip select latched into the rising edge of the clock input (ck). when the latched value is low, memory is activated. xwe write enable latched into the rising edge of the clock input (ck). memory is activated for write operation when the latched value is low, or for read operation when the latched value is high. xbwen byte write enable latched into the rising edge of the clock input (ck). each byte of data is assigned one byte write enable signal. only data bytes with low byte xbwen when xwe is low, are written to memory. xbwe0 for d0?d7 xbwe1 for d8?d15 xbwe2 for d16?d23 xbwe3 for d24?d31 a0 to an address input latched into the rising edge of the clock input (ck). d0 to dn data input the write data is latched into the rising edge of the clock input (ck) and written to memory cells. y0 to yn data output during reading, the data from memory cells is output a finite access time after the rising edge of the clock input (ck). during writing, the latched write data is output from these pins. block diagram an a1 a0 ck xcs xwe address buffer row decoder memory cell arra y column decoder data i/o buffer control xbwen dn yn xbwe0 d0 y0 s1x60k 1 port ram (byte write option) chapter 6 memory blocks embedded array S1X60000 series epson 143 design guide 6.3.4 truth table of device operation for writing, assert chip select (xcs), write enable (xwe), and byte write enable (xbwe0 to xbwe3) (by pulling them low), and set the address inputs (a0 to an) and data inputs (d0 to dn) before the clock input (ck) goes high. all of the chip select, write enable, byte write enable, address input, and data input signals are latched into the rising edge of the clock input, at which time memory is activated for write operation. during this period, the data being written is output from the data output pins (y0 to yn). the write operation finishes at the fall of the clock, with the input signals unlatched and the memory placed in standby state. for reading, assert chip select (xcs) and deassert write enable (xwe) (by pulling xcs low and xwe high), and set the address inputs (a0 to an) before the clock input (ck) goes high. all of the chip select, write enable, and address input, and data input signals are latched into the rising edge of the clock input, at which time memory is activated for read operation. during this period, data is output from the data output pins (y0 to yn) a finite access time after the rise of the clock. the read operation finishes at the fall of the clock, with the input signals unlatched and the memory placed in standby state. for either reading or writing, data appears at the data output pins even after the operation has been completed and the memory is placed in standby state. truth table of standard type 1 port ram operation ck xcs xwe xbwe0 xbwe1 xbwe2 xbwe3 write output state operation mode l x x x x x x ? data hold standby l h l h x x x x ? read data read l h l l l l l l d0 to d31 write data write all bytes l h l l l h h h d0 to d7 write data (*1) write 1st byte l h l l h l h h d8 to d15 write data (*1) write 2nd byte l h l l h h l h d16 to d23 write data (*1) write 3rd byte l h l l h h h l d24 tod31 write data (*1) write 4th byte l h l l h h h h ? write data (*1) unable to write l h h x x x x x ? data hold standby h l x x x x x x ? data hold standby note *1: the state of the data outputs (y0 to yn) reflects the values supplied to the data inputs (d0 to dn). however, only the data bytes selected using byte write enable (xbwe0 to xbwe3) are written to memory. data bytes unselected using byte write enable are not written to memory. chapter 6 memory blocks 144 epson embedded array S1X60000 series design guide 6.3.5 timing charts read cycle a ddress ck xcs xwe xbwen data out standby standby read t cyc stable t as t ah t css t csh t ckl t ckh t wes t weh t oh old data valid data t ack write cycle a ddress ck xcs xwe xbwen data out standb y standb y read t cyc stable t as t ah t css t csh t ckl t ckh t wdh old data through data t wdt data in t wes t weh t bwes t bweh t ds t dh stable chapter 6 memory blocks embedded array S1X60000 series epson 145 design guide 6.3.6 electrical characteristics power consumption (memory configuration: 8 k words 8 data) 2.5 v 0.2 v -40 to +85 c 2.0 v 0.2 v -40 to +85 c parameter symbol min. typ. max. min. typ. max. unit standby current idds ? 1000 ? ? 700 ? na active current idda ? 160 ? ? 130 ? a/mhz ac characteristics 2.5 v 0.2 v -40 to +85 c 2.0 v 0.2 v -40 to +85 c parameter symbol min. typ. max. min. typ. max. unit clock frequency fc ? ? 125 ? ? 75 mhz ck access time t ack ? 3.4 6.2 ? 4.8 9.6 ns ck high width time t ckh 4.0 ? ? 6.6 ? ? ns ck low width time t ckl 3.2 ? ? 4.4 ? ? ns cycle time t cyc 8.0 ? ? 13.2 ? ? ns cs setup time t css 2.6 ? ? 4.2 ? ? ns cs hold time t csh 0 ? ? 0 ? ? ns address setup time t as 2.6 ? ? 4.2 ? ? ns address hold time t ah 0 ? ? 0 ? ? ns we setup time t wes 2.6 ? ? 4.2 ? ? ns we hold time t weh 0 ? ? 0 ? ? ns bwe setup time t bwes 2.6 ? ? 4.2 ? ? ns bwe hold time t bweh 0 ? ? 0 ? ? ns output hold time t oh 1.0 ? ? 1.8 ? ? ns data setup time t ds 2.6 ? ? 4.2 ? ? ns data hold time t dh 0 ? ? 0 ? ? ns write data hold time t wdh 0.3 ? ? 0.5 ? ? ns write data through time t wdt ? ? 3.0 ? ? 4.2 ns chapter 6 memory blocks 146 epson embedded array S1X60000 series design guide power consumption (memory configuration: 8 k words 8 data) 2.5 v 0.2 v 0 to +70 c 2.0 v 0.2 v 0 to +70 c parameter symbol min. typ. max. min. typ. max. unit standby current idds ? ? ? ? ? ? na active current idda ? 160 ? ? 130 ? a/mhz ac characteristic 2.5 v 0.2 v 0 to +70 c 2.0 v 0.2 v 0 to +70 c parameter symbol min. typ. max. min. typ. max. unit clock frequency fc ? ? 135 ? ? 78 mhz ck access time t ack ? 3.4 5.8 ? 4.8 9.2 ns ck high width time t ckh 3.8 ? ? 6.4 ? ? ns ck low width time t ckl 3.0 ? ? 4.0 ? ? ns cycle time t cyc 7.6 ? ? 12.8 ? ? ns cs setup time t css 2.4 ? ? 4.0 ? ? ns cs hold time t csh 0 ? ? 0 ? ? ns address setup time t as 2.4 ? ? 4.0 ? ? ns address hold time t ah 0 ? ? 0 ? ? ns we setup time t wes 2.4 ? ? 4.0 ? ? ns we hold time t weh 0 ? ? 0 ? ? ns bwe setup time t bwes 2.4 ? ? 4.0 ? ? ns bwe hold time t bweh 0 ? ? 0 ? ? ns output hold time t oh 1.0 ? ? 1.8 ? ? ns data setup time t ds 2.4 ? ? 4.0 ? ? ns data hold time t dh 0 ? ? 0 ? ? ns write data hold time t wdh 0.3 ? ? 0.5 ? ? ns write data through time t wdt ? ? 2.8 ? ? 4.0 ns chapter 6 memory blocks embedded array S1X60000 series epson 147 design guide 6.4 standard type dual port ram 6.4.1 features ? for this type of ram, the circuit and layout pattern are exclusively designed as dual port ram in order to reduce the area that the ram occupies. (three al layers are used.) ? can be configured in a wide range of memory capacities (1k to 64k bits), and provides superior flexibility for selection of the height to width ratio of the layout shape. furthermore, if large-capacity memory is required, multiple pieces of memory macros may be used. ? can be accessed at high speed and consumes less current than other rams of the same class. ? a byte write function is included, allowing the bits of write data to be selected in byte units. ? the chip select, write enable, byte write enable, address, and data input/output parts contain a latch circuit, making the ram capable of clock-synchronized, high-speed operation. ? the data input port and data output port are separated. ? the data output part contains a latch circuit, so that readout data is output continuously until the next read cycle. 6.4.2 ram sizes the sizes of standard type dual port rams vary in a complicated manner depending on the word/bit configurations. for detailed information on ram sizes, please contact the sales division of epson. chapter 6 memory blocks 148 epson embedded array S1X60000 series design guide 6.4.3 input signals and block diagrams ports 1 and 2 are each capable of performing read and write operations. each port comes equipped with a clock input pin, allowing them to be operated with different frequencies or timing independently of each other. be aware that no memory cells can be accessed from two ports at the same time. if arbitration facilities, busy signals, or the like are required to resolve conflicts, configure a necessary circuit in the gate-array section external to the macro. (if accessed at the same time, the read or write operation in that cycle and the data in the accessed memory cell become indeterminate.) port-1 signals (read/write) input/output signal symbol name description cka clock input chip select (xcsa), write enable (xwea), byte write enable (xbwean), address input (aa0 to aan), and data input (da0 to dan) are latched into the rising edge (low to high transition) of the clock input (cka). memory is activated when the latched chip select signal is low. while the memory is active, data is written to memory when the latched write enable signal is low or read from memory when the signal is high. operation finishes on the next fall of the clock. xcsa chip select latched into the rising edge of the clock input (cka). memory is activated when the latched value is low. xwea write enable latched into the rising edge of the clock input (cka). memory is activated for write operation when the latched value is low or for read operation when the latched value is high. xbwean byte write enable latched into the rising edge of the clock input (cka). each byte of data is assigned one byte write enable signal. only data bytes with low byte xbwean when xwea is low are written to memory. xbwea0 for da0?da7 xbwea1 for da8?da15 xbwea2 for da16?da23 xbwea3 for da24?da31 aa0 to aan address input latched into the rising edge of the clock input (cka). da0 to dan data input the write data is latched into the rising edge of the clock input (cka) and written to memory cells. ya0 to yan data output during reading, the data from memory cells is output a finite access time after the rising edge of the clock input (cka). during writing, the latched write data is output from these pins. chapter 6 memory blocks embedded array S1X60000 series epson 149 design guide port-2 signals (read/write) input/output signal symbol name description ckb clock input chip select (xcsb), write enable (xweb), byte write enable (xbwebn), address input (ab0 to abn), and data input (db0 to dbn) are latched into the rising edge (low to high transition) of the clock input (ckb). memory is activated when the latched chip select signal is low. while the memory is active, data is written to memory when the latched write enable signal is low or read from memory when the signal is high. operation finishes on the next fall of the clock. xcsb chip select latched into the rising edge of the clock input (ckb). memory is activated when the latched value is low. xweb write enable latched into the rising edge of the clock input (ckb). memory is activated for write operation when the latched value is low or for read operation when the latched value is high. xbwebn byte write enable latched into the rising edge of the clock input (ckb). each byte of data is assigned one byte write enable signal. only data bytes with low byte xbwebn when xweb is low are written to memory. xbweb0 for db0?db7 xbweb1 for db8?db15 xbweb2 for db16?db23 xbweb3 for db24?db31 ab0 to abn address input latched into the rising edge of the clock input (ckb). db0 to dbn data input the write data is latched into the rising edge of the clock input (ckb) and written to memory cells. yb0 to ybn data output during reading, the data from memory cells is output a finite access time after the rising edge of the clock input (ckb). during writing, the latched write data is output from these pins. block diagram memory cell array colu mn dec oder row dec oder address buffer data i/o buffer contr ol aa0 aa1 aan cka xcsa xw ea colu mn dec oder data i/o buffer row dec oder address buff er contr ol ab0 ab1 abn ckb xcsb xweb contr ol contr ol s1x60k dual port ram (byte write option) ya0 da0 yan dan xbwea0 xbwean yb0 db0 ybn dbn xbweb0 xbwebn chapter 6 memory blocks 150 epson embedded array S1X60000 series design guide 6.4.4 truth table of device operation for writing, assert chip select (xcsa or xcsb), write enable (xwea or xweb), and byte write enable (xbwea0 to xbwea3 or xbweb0 to xbweb3) (by pulling them low), and set the address inputs (aa0 to aan or ab0 to abn) and data inputs (da0 to dan or db0 to dbn) before the clock input (cka or ckb) goes high. all of the chip select, write enable, byte write enable, address input, and data input signals are latched into the rising edge of the clock input, at which time memory is activated for write operation. during this period, the data being written is output from the data output pins (ya0 to yan or yb0 to ybn). the write operation finishes at the fall of the clock, with the input signals unlatched and the memory placed in standby state. for reading, assert chip select (xcsa or xcsb) and deassert write enable (xwea or xweb) (by pulling xcsa or xcsb low and xwea or xweb high), and set the address inputs (aa0 to aan or ab0 to abn) before the clock input (cka or ckb) goes high. all of the chip select, write enable, and address-input signals are latched into the rising edge of the clock input, at which time memory is activated for read operation. during this period, data is output from the output pins (ya0 to yan or yb0 to ybn) a finite access time after the rise of the clock. the read operation finishes at the fall of the clock, with the input signals unlatched and the memory placed in standby state. for either read or write, data appears at the data output pins even after the operation has completed and the memory is placed in standby state. port-1 truth table cka xcsa xwea xbwea0 xbwea1 xbwea2 xbwea3 write output state operation mode l x x x x x x ? data hold standby l h l h x x x x ? read data read l h l l l l l l da0 ? da31 write data write all bytes l h l l l h h h da0 ? da7 write data (*1) write 1st byte l h l l h l h h da8 ? da15 write data (*1) write 2nd byte l h l l h h l h da16 ? da23 write data (*1) write 3rd byte l h l l h h h l da24 ? da31 write data (*1) write 4th byte l h l l h h h h ? write data (*1) unable to write l h h x x x x x ? data hold standby h l x x x x x x ? data hold standby port-2 truth table ckb xcsb xweb xbweb0 xbweb1 xbweb2 xbweb3 write output state operation mode l x x x x x x ? data hold standby l h l h x x x x ? read data read l h l l l l l l db0 ? db31 write data write all bytes l h l l l h h h db0 ? db7 write data (*1) write 1st byte l h l l h l h h db8 ? db15 write data (*1) write 2nd byte l h l l h h l h db16 ? db23 write data (*1) write 3rd byte l h l l h h h l db24 ? db31 write data (*1) write 4th byte l h l l h h h h ? write data (*1) unable to write l h h x x x x x ? data hold standby h l x x x x x x ? data hold standby note *1: the state of the data outputs (ya0 to yan or yb0 to ybn) reflects the values supplied to the data inputs (da0 to dan or db0 to dbn). however, only the data bytes selected using byte write enable (xbwea0 to xbwea3 or xbweb0 to xbweb3) are written to memory. data bytes unselected using byte write enable are not written to memory. chapter 6 memory blocks embedded array S1X60000 series epson 151 design guide 6.4.5 timing charts port 1 t wes t weh t oh old data valid data t ack write cycle a ddress ck a xcs a xwe a xbwe a n data out standb y standb y read t cyc stable t as t ah t css t csh t ckl t ckh t wdh old data through data t wdt data in t wes t weh t bwes t bweh t ds t dh stable read cycle a ddress ck a xcs a xwe a xbwe a n data out standby standby read t cyc stable t as t ah t css t csh t ckl t ckh chapter 6 memory blocks 152 epson embedded array S1X60000 series design guide port 2 read cycle a ddress ck a xcs a xwe a xbwe a n data out standby standby read t cyc stable t as t ah t css t csh t ckl t ckh t wes t weh t oh old data valid data t ack write cycle a ddress ck a xcs a xwe a xbwe a n data out standb y standb y read t cyc stable t as t ah t css t csh t ckl t ckh t wdh old data through data t wdt data in t wes t weh t bwes t bweh t ds t dh stable chapter 6 memory blocks embedded array S1X60000 series epson 153 design guide 6.4.6 electrical characteristics power consumption (memory configuration: 8 k words 8 data) 2.5 v 0.2 v -40 to +85 c 2.0 v 0.2 v -40 to +85 c parameter symbol min. typ. max. min. typ. max. unit standby current idds ? ? ? ? na active current idda ? 260 ? 210 a/mhz ac characteristics 2.5 v 0.2 v -40 to +85 c 2.0 v 0.2 v -40 to +85 c parameter symbol min. typ. max. min. typ. max. unit clock frequency fc ? ? 119 ? ? 71 mhz ck access time t ack ? 4.0 7.2 ? 5.4 10.8 ns ck high width time t ckh 4.2 ? ? 7.0 ? ? ns ck low width time t ckl 3.6 ? ? 5.4 ? ? ns cycle time t cyc 8.4 ? ? 14.0 ? ? ns cs setup time t css 3.8 ? ? 5.0 ? ? ns cs hold time t csh 0 ? ? 0 ? ? ns address setup time t as 3.8 ? ? 5.0 ? ? ns address hold time t ah 0 ? ? 0 ? ? ns we setup time t wes 3.8 ? ? 5.0 ? ? ns we hold time t weh 0 ? ? 0 ? ? ns bwe setup time t bwes 3.8 ? ? 5.0 ? ? ns bwe hold time t bweh 0 ? ? 0 ? ? ns output hold time t oh 1.0 ? ? 2.0 ? ? ns data setup time t ds 3.8 ? ? 5.0 ? ? ns data hold time t dh 0 ? ? 0 ? ? ns write data hold time t wdh 0.3 ? ? 0.5 ? ? ns write data through time t wdt ? ? 3.8 ? ? 5.2 ns chapter 6 memory blocks 154 epson embedded array S1X60000 series design guide power consumption (memory configuration: 8 k words 8 data) 2.5 v 0.2 v 0 to +70 c 2.0 v 0.2 v 0 to +70 c parameter symbol min. typ. max. min. typ. max. unit standby current idds ? ? ? ? na active current idda ? 260 ? 210 a/mhz ac characteristics 2.5 v 0.2 v 0 to +70 c 2.0 v 0.2 v 0 to +70 c parameter symbol min. typ. max. min. typ. max. unit clock frequency fc ? ? 128 ? ? 74 mhz ck access time t ack ? 4.0 6.8 ? 5.4 10.4 ns ck high width time t ckh 4.0 ? ? 6.8 ? ? ns ck low width time t ckl 3.6 ? ? 5.0 ? ? ns cycle time t cyc 8.0 ? ? 13.6 ? ? ns cs setup time t css 3.8 ? ? 4.8 ? ? ns cs hold time t csh 0 ? ? 0 ? ? ns address setup time t as 3.8 ? ? 4.8 ? ? ns address hold time t ah 0 ? ? 0 ? ? ns we setup time t wes 3.8 ? ? 4.8 ? ? ns we hold time t weh 0 ? ? 0 ? ? ns bwe setup time t bwes 3.8 ? ? 4.8 ? ? ns bwe hold time t bweh 0 ? ? 0 ? ? ns output hold time t oh 1.0 ? ? 2.0 ? ? ns data setup time t ds 3.8 ? ? 4.8 ? ? ns data hold time t dh 0 ? ? 0 ? ? ns write data hold time t wdh 0.3 ? ? 0.5 ? ? ns write data through time t wdt ? ? 3.6 ? ? 5.0 ns chapter 6 memory blocks embedded array S1X60000 series epson 155 design guide 6.5 high density type 1 port ram 6.5.1 features ? for this type of ram, the circuit and layout pattern are exclusively designed as 1 port ram in order to reduce the area that the ram occupies. ? can be accessed at high speed and consumes less current than other rams of the same class. ? the chip select, write enable, address, data and byte write enable input parts contain a latch circuit, making the ram capable of clock synchronized, high speed operation. ? the data input port and data output port are separated. ? a byte write function is included, allowing the bits of write data to be selected in byte units. ? the data output part contains a latch circuit, allowing readout data to be output continuously until the next read cycle. 6.5.2 ram sizes the sizes of high density type 1 port rams vary in a complicated manner, depending on the word/bit configurations. for detailed information on ram sizes, please contact the sales division of epson. chapter 6 memory blocks 156 epson embedded array S1X60000 series design guide 6.5.3 input/output signals and block diagrams input/output signal symbol name description ck clock input chip select (xcs), write enable (xwe), byte write enable (xbwen), address input (a0 to an), and data input (d0 to dn) are latched into the rising edge (low to high transition) of the clock input (ck). memory is activated when the latched chip select signal is low. while the memory is active, data is written to memory when the latched write enable signal is low or read from memory when the signal is high. operation finishes on the next fall of the clock. xcs chip select latched into the rising edge of the clock input (ck). memory is activated when the latched value is low. xwe write enable latched into the rising edge of the clock input (ck). memory is activated for write operation when the latched value is low or for read operation when the latched value is high. xbwen byte write enable latched into the rising edge of the clock input (ck). each byte of data is assigned one byte write enable signal. only data bytes with low xbwen when xwe is low are written to memory. xbwe0 for d0 to d7 xbwe1 for d8 to d15 xbwe2 for d16 to d23 xbwe3 for d24 to d31 a0 to an address input latched into the rising edge of the clock input (ck). d0 to dn data input the write data is latched into the rising edge of the clock input (ck) and written to memory cells. y0 to yn data output during reading, the data from memory cells is output a finite access time after the rising edge of the clock input (ck). during writing, the latched write data is output from these pins. block diagram an a1 a0 ck xcs xwe address buffer row decoder memory cell array column decoder data i/o buffer control xbwen dn yn xbwe0 d0 y0 s1x60k high density 1 port ram (byte write option) chapter 6 memory blocks embedded array S1X60000 series epson 157 design guide 6.5.4 truth table of device operation for writing, assert chip select (xcs), write enable (xwe), and byte write enable (xbwe0 to xbwe3) (by pulling them low), and set the address inputs (a0 to an) and data inputs (d0 to dn) before the clock input (ck) goes high. all of the chip select, write enable, byte write enable, address input, and data input signals are latched into the rising edge of the clock input, at which time memory is activated for write operation. during this period, the data being written is output from the data output pins (y0 to yn). the write operation finishes at the fall of the clock, with the input signals unlatched and the memory placed in standby state. for reading, assert chip select (xcs) and deassert write enable (xwe) (by pulling xcs low and xwe high), and set the address inputs (a0 to an) before the clock input (ck) goes high. all of the chip select, write enable, and address input signals are latched into the rising edge of the clock input, at which time memory is activated for read operation. during this period, data is output from the data output pins (y0 to yn) a finite access time after the rise of the clock. the read operation finishes at the fall of the clock, with the input signals unlatched and the memory placed in standby state. for either read or write, data appears at the data output pins even after the operation has completed and the memory is placed in standby state. truth table of high density type 1 port ram operation ck xcs xwe xbwe0 xbwe1 xbwe2 xbwe3 write output state operation mode l x x x x x x ? data hold standby l h l h x x x x ? read data read l h l l l l l l d0 to d31 write data write all bytes l h l l l h h h d0 to d7 write data (*1) write 1st byte l h l l h l h h d8 to d15 write data (*1) write 2nd byte l h l l h h l h d16 to d23 write data (*1) write 3rd byte l h l l h h h l d24 to d31 write data (*1) write 4th byte l h l l h h h h ? write data (*1) unable to write l h h x x x x x ? data hold standby h l x x x x x x ? data hold standby note *1: the state of data outputs (y0 to yn) reflects the values supplied to data inputs (d0 to dn). however, only the data bytes selected using byte write enable (xbwe0 to xbwe3) are written to memory. data bytes unselected using byte write enable are not written to memory. chapter 6 memory blocks 158 epson embedded array S1X60000 series design guide 6.5.5 timing charts read cycle a ddress ck xcs xwe xbwen data out standby standby read t cyc stable t as t ah t css t csh t ckl t ckh t wes t weh t oh old data valid data t ack write cycle a ddress ck xcs xwe xbwen data out standby standby read t cyc stable t as t ah t css t csh t ckl t ckh t wdh old data through data t wdt data in t wes t weh t bwes t bweh t ds t dh stable chapter 6 memory blocks embedded array S1X60000 series epson 159 design guide 6.5.6 electrical characteristics power consumption (memory configuration: 32 k words 16 data) 2.5 v 0.2 v -40 to +85 c 2.0 v 0.2 v -40 to +85 c parameter symbol min. typ. max. min. typ. max. unit standby current idds ? ? ? ? ? ? na active current idda ? 250 ? ? 200 ? a/mhz ac characteristics 2.5 v 0.2 v -40 to +85 c 2.0 v 0.2 v -40 to +85 c parameter symbol min. typ. max. min. typ. max. unit clock frequency fc ? ? 71 ? ? 40 mhz ck access time t ack ? 5.8 10.8 ? 8.2 17.2 ns ck high width time t ckh 7.0 ? ? 12.2 ? ? ns ck low width time t ckl 3.6 ? ? 4.0 ? ? ns cycle time t cyc 14.0 ? ? 24.4 ? ? ns cs setup time t css 2.2 ? ? 3.8 ? ? ns cs hold time t csh 0 ? ? 0 ? ? ns address setup time t as 2.2 ? ? 3.8 ? ? ns address hold time t ah 0 ? ? 0 ? ? ns we setup time t wes 2.2 ? ? 3.8 ? ? ns we hold time t weh 0 ? ? 0 ? ? ns bwe setup time t bwes 2.2 ? ? 3.8 ? ? ns bwe hold time t bweh 0 ? ? 0 ? ? ns output hold time t oh 2.6 ? ? 4.0 ? ? ns data setup time t ds 2.2 ? ? 3.8 ? ? ns data hold time t dh 0 ? ? 0 ? ? ns write data hold time t wdh 1.0 ? ? 1.2 ? ? ns write data through time t wdt ? ? 4.0 ? ? 6.6 ns chapter 6 memory blocks 160 epson embedded array S1X60000 series design guide power consumption (memory configuration: 32 k words 16 data) 2.5 v 0.2 v 0 to +70 c 2.0 v 0.2 v 0 to +70 c parameter symbol min. typ. max. min. typ. max. unit standby current idds ? ? ? ? ? ? na active current idda ? 250 ? ? 200 ? a/mhz ac characteristics 2.5 v 0.2 v 0 to +70 c 2.0 v 0.2 v 0 to +70 c parameter symbol min. typ. max. min. typ. max. unit clock frequency fc ? ? 76 ? ? 42 mhz ck access time t ack ? 5.8 10.0 ? 8.2 16.4 ns ck high width time t ckh 6.6 ? ? 11.8 ? ? ns ck low width time t ckl 3.2 ? ? 3.8 ? ? ns cycle time t cyc 13.2 ? ? 23.6 ? ? ns cs setup time t css 2.2 ? ? 3.8 ? ? ns cs hold time t csh 0 ? ? 0 ? ? ns address setup time t as 2.0 ? ? 3.8 ? ? ns address hold time t ah 0 ? ? 0 ? ? ns we setup time t wes 2.0 ? ? 3.8 ? ? ns we hold time t weh 0 ? ? 0 ? ? ns bwe setup time t bwes 2.0 ? ? 3.8 ? ? ns bwe hold time t bweh 0 ? ? 0 ? ? ns output hold time t oh 2.6 ? ? 4.0 ? ? ns data setup time t ds 2.0 ? ? 3.8 ? ? ns data hold time t dh 0 ? ? 0 ? ? ns write data hold time t wdh 1.0 ? ? 1.2 ? ? ns write data through time t wdt ? ? 3.8 ? ? 6.2 ns chapter 6 memory blocks embedded array S1X60000 series epson 161 design guide 6.6 mask rom 6.6.1 features ? the circuit and layout pattern are exclusively designed as mask rom in order to reduce the area that it occupies (three al layers are used.) ? because data is programmed into memory at nearly the end of the manufacturing process (hola), tat can be reduced. ? can be configured in a wide range of memory capacities (1 k to 256 k bits), and provides superior flexibility for selection of the height to width ratio of the layout shape. furthermore, if large-capacity memory is required, multiple pieces of memory macros may be used. ? can be accessed at high speed and consumes less current than other roms of the same class. ? can operate with low voltage over a wide voltage range. ? the chip select and address-input parts contain a latch circuit, making the rom capable of clock synchronized, high speed operation. ? the data output part contains a latch circuit, allowing readout data to be output continuously until the next read cycle. 6.6.2 rom sizes the rom sizes vary in a complicated manner depending on the word/bit configurations. for detailed information on rom sizes, please contact the sales division of epson. chapter 6 memory blocks 162 epson embedded array S1X60000 series design guide 6.6.3 input/output signals and block diagrams input/output signal symbol name description ck clock input chip select (xcs) and address input (a0?an) are latched into the rising edge (low to high transition) of the clock input (ck). when the latched chip select signal is low, memory is activated for read operation. xcs chip select latched into the rising edge of the clock input (ck). when this latched value is low, memory is activated for read operation. a0 to an address input latched into the rising edge of the clock input (ck). y0 to yn data output the data readout from memory cells is output from these pins a finite access time after the rising edge of the clock input (ck). block diagram an a1 a0 ck xcs address buffer row decoder memory cell arra y column decoder data i/o buffer control y0 y1 yn S1X60000 mask rom chapter 6 memory blocks embedded array S1X60000 series epson 163 design guide 6.6.4 truth table of device operation for reading, assert chip select (xcs) (by pulling it low), and set the address inputs (a0 to an) before the clock input (ck) goes high. the chip select and address input signals are latched into the rising edge of the clock, at which time memory is activated for read operation. during this period, data is output from the data output pins a finite access time after the rise of the clock. the read operation finishes at the fall of the clock, with the input signals unlatched and the memory placed in standby state. even after the read operation has completed and the memory is placed in standby state, data remains displayed at the data output pins. truth table of rom operation ck xcs output state operation mode l x data hold standby l h l read data read l h h data hold standby h l x data hold standby 6.6.5 timing charts read cycle a ddress ck xcs data out standby standby read t cyc stable t as t css t csh t ckl t ckh t oh old data valid data t ack t ah chapter 6 memory blocks 164 epson embedded array S1X60000 series design guide 6.6.6 electrical characteristics power consumption (memory configuration: 32 k words 8 data) 2.5 v 0.2 v -40 to +85 c 2.0 v 0.2 v -40 to +85 c parameter symbol min. typ. max. min. typ. max. unit standby current idds ? ? ? ? ? ? na active current idda ? 175 ? ? 130 ? a/mhz ac characteristics 2.5 v 0.2 v -40 to +85 c 2.0 v 0.2 v -40 to +85 c parameter symbol min. typ. max. min. typ. max. unit clock frequency fc ? ? 66 ? ? 40 mhz ck access time t ack ? 5.4 9.4 ? 7.0 14.0 ns ck high width time t ckh 7.6 ? ? 12.4 ? ? ns ck low width time t ckl 2.8 ? ? 3.2 ? ? ns cycle time t cyc 15.2 ? ? 24.8 ? ? ns cs setup time t css 2.6 ? ? 3.0 ? ? ns cs hold time t csh 0 ? ? 0 ? ? ns address setup time t as 2.6 ? ? 3.0 ? ? ns address hold time t ah 0 ? ? 0 ? ? ns output hold time t oh 1.0 ? ? 2.0 ? ? ns power consumption (memory configuration: 32 k words 16 data) 2.5 v 0.2 v 0 to +70 c 2.0 v 0.2 v 0 to +70 c parameter symbol min. typ. max. min. typ. max. unit standby current idds ? ? ? ? ? ? na active current idda ? 175 ? ? 130 ? a/mhz chapter 6 memory blocks embedded array S1X60000 series epson 165 design guide ac characteristics 2.5 v 0.2 v 0 to +70 c 2.0 v 0.2 v 0 to +70 c parameter symbol min. typ. max. min. typ. max. unit clock frequency fc ? ? 71 ? ? 42 mhz ck access time t ack ? 5.4 8.6 ? 7.0 13.2 ns ck high width time t ckh 7.0 ? ? 12.0 ? ? ns ck low width time t ckl 2.6 ? ? 3.0 ? ? ns cycle time t cyc 14.0 ? ? 24.0 ? ? ns cs setup time t css 2.4 ? ? 2.8 ? ? ns cs hold time t csh 0 ? ? 0 ? ? ns address setup time t as 2.4 ? ? 2.8 ? ? ns address hold time t ah 0 ? ? 0 ? ? ns output hold time t oh 1.0 ? ? 2.0 ? ? ns 6.7 access to nonexistent addresses inhibited when some rams with an intermediate word configuration (e.g., 48 or 88 words) are used, there is a possibility of accessing nonexistent addresses. in the actual ic, if nonexistent addresses are accessed for reading, the target word lines do not exist and all word lines are turned off, resulting in all bit lines being placed in a floating state. for this reason, the following problems may occur: (1) because read operation is performed while all bit lines are left floating, all bits of ram output become ?indeterminate.? (2) because read operation is performed while all bit lines are left floating, a path is created in part of the circuit through which current can flow. although the amount of this current depends on the ram configuration and size, it causes the operating and quiescent currents of the entire ic to vary. therefore, we recommend that access to nonexistent addresses be inhibited. in logic simulation, the presence of nonexistent addresses is checked synchronously with the rising edge of the clock during read/write operation and, when access to any nonexistent address is attempted, a timing error is output. chapter 7 propagation delay and timing 166 epson embedded array S1X60000 series design guide chapter 7 propagation delay and timing 7.1 accuracy of the propagation delay time the propagation delay time, t pd , varies with the lsi?s power supply voltage, ambient temperature, and process conditions. it also varies with circuit configurations such as the output load (e.g., wiring capacitance or fan-out counts), distorted input waveforms, input logic levels, and mirror effects. for the S1X60000 series, a delay calculator has been introduced that helps minimize these fluctuating factors, in order to provide a highly accurate delay time calculation environment. therefore, be aware that the results obtained using this delay calculator do not necessarily match the propagation delay times calculated by customers from the values listed in the ?S1X60000 series cell library? by following the simplified calculation procedure described below. 7.2 calculating the propagation delay time the calculation formulas shown below provide a simple means of calculating the propagation delay time. this calculation formula is such that the larger the load capacitance, the greater the delay error, so that the resulting values are smaller than those obtained using the delay calculator. therefore, the values calculated here can only be used as a guide. (1) delay time of input cells and internal cells the delay time of input cells and internal cells, t pd , is calculated as the sum total of the cell?s inherent delay time when nonloaded, t 0 , and the load delay caused by the wiring load capacitance and input load capacitance connected to the cell outputs. consequently, the propagation delay time, t pd , is calculated using the equation below. t pd = t 0 + k ( load a + load b) .......... (equation 7-1) where, t 0 : cell?s inherent delay when nonloaded [ps] k : load delay coefficient [ps/lu] load a : input capacitance of the connected cell [lu] load b : wiring load capacitance [lu] note 1: the values of t 0 and k vary with the lsi?s operating voltage, ambient temperature, and process conditions. for these parameters, use the values listed in the ?S1X60000 series cell library.? note 2: the unit ?lu? stands for load unit. in the S1X60000 series, the gate capacitance at the input pin of the inverter cell (in1) is defined as 1 lu. (2) delay time of the output cells the delay time of the output cells, t pd , is calculated from the output cell?s inherent delay time when nonloaded, t 0 , and the load capacitance connected to the external output pins, c l , by using the equation below. t pd = t 0 + k c l / 10 ........ (equation 7-2) where, t 0 : output cell?s inherent delay when nonloaded [ps] k : output cell?s load delay coefficient [ps/10 pf] cl : load capacitance connected to the external output pins [pf] chapter 7 propagation delay and timing embedded array S1X60000 series epson 167 design guide 7.3 virtual wiring capacitance as placement and routing performed in the circuit design phase are not based on the circuit?s connection information, the length of the wiring connected as a load to the circuit has not yet been determined. for this reason, in the pre placement and routing stages, the propagation delay time is calculated using the wiring capacitances (referred to as the ?virtual wiring capacitances?) that have been prepared through statistical processing. for the S1X60000 series, a wide selection of virtual wiring capacitances per branch of output are available to choose from depending on the number of wiring layers and gate counts. these virtual wiring capacitances are listed in tables 7-1. table 7-1 virtual wiring capacitances per branch (unit: lu) gate counts 3-layer wiring 4-layer wiring 5-layer wiring 1000 2.056 2.062 2.057 5000 2.063 2.068 2.064 10000 2.071 2.076 2.072 20000 2.087 2.092 2.088 40000 2.119 2.125 2.120 60000 2.152 2.157 2.153 80000 2.184 2.190 2.185 100000 2.217 2.222 2.218 200000 2.379 2.385 2.380 400000 2.703 2.710 2.704 600000 3.027 3.035 3.029 800000 3.351 3.360 3.353 1000000 3.675 3.685 3.677 1200000 3.999 4.010 4.001 1400000 4.323 4.335 4.326 1600000 4.648 4.660 4.650 1800000 4.972 4.985 4.974 2000000 5.296 5.310 5.299 chapter 7 propagation delay and timing 168 epson embedded array S1X60000 series design guide examples of calculation of the propagation delay time examples of calculation of the propagation delay time examples of calculation of the propagation delay time examples of calculation of the propagation delay time (1) delay time of input cells and internal cells the following describes the procedure for calculating the approximate amount of propagation delay time in each path, using the circuits in figure 7-1 as an example. table 7-2 lists various characteristic values excerpted from the ?S1X60000 series cell library.? the circuits shown below amount to a total of 20,000 gates in circuit size. a na2 in1 no2 in2 a1 a a1 xx x x in out1 out2 out3 out0 figure 7-1 example circuits for calculation of the internal cell propagation delay time table 7-2 delay characteristics of each cell (power supply voltage: 2.5 v) input output delay characteristics (typ.) cell pin fan-in [lu] pin fan-out [lu] from to parameter t 0 [ps] k [ps/lu] t plh 43 18.7 in1 a 1.0 x 14.4 a x t phl 44 10.2 t plh 36 9.3 in2 a 2.0 x 28.9 a x t phl 37 5.1 t plh 57 18.9 na2 a1 0.9 x 14.2 a x t phl 50 16.0 t plh 56 36.0 no2 a1 1.1 x 7.3 a x t phl 53 10.2 in2 (pin a), na2 (pin a1), and no2 (pin a1) are connected to output pin x of the cell in1. therefore, from table 7-2, the total amount of the input load capacitance of the cells, load a, is found to be as follows: load a = in2 (fan-in of pin a) + na2 (fan-in of pin a1) + no2 (fan-in of pin a1) = 2.0 + 0.9 + 1.1 = 4.0 [lu] chapter 7 propagation delay and timing embedded array S1X60000 series epson 169 design guide in addition, the wiring load capacitance, load b, is calculated using the virtual wiring capacitances. here, assuming that placement and routing are performed using 3 layer wiring, the virtual wiring capacitances of 20,000 gates in circuit size are found to be 2.087 [lu] from table 7-1. because output pin x of the cell l1inx1 branches to three inputs, the wiring load capacitance, load b, is calculated as follows: load b = 2.087 3 = 6.261 [lu] therefore, the delay in in1 under typ. conditions is calculated using equation 7-1 as shown below. here, the symbol ? ? denotes the rise, and the symbol ? ? denotes the fall. the rise and fall here refer to the rising and falling transitions at output pin x. t pd (a x ) = t 0 ( ) + k ( ) ( load a + load b) = 43 + 18.7 (4.0 + 6.261) = 234.9 [ps] t pd (a x ) = t 0 ( ) + k ( ) ( load a + load b) = 44 + 10.2 (4.0 + 6.261) = 148.7 [ps] next, calculate the path delay from in to out1, out2, and out3. in this case, because out1, out2, and out3 are in a nonloaded state, the cell?s inherent delay must be added to the above delay value. in the calculation of this path delay, furthermore, care must be taken with respect to the rise and fall of each output. 1) delay in in out1 path = in1 (a x delay) + in2 (a x delay) t pd (in out1 ) = t pd (in out0 ) + t pd (out0 out1 ) = 148.7 + 36 = 184.7 [ps] t pd (in out1 ) = t pd (in out0 ) + t pd (out0 out1 ) = 234.9 + 37 = 271.9 [ps] 2) delay in in out2 path = in1 (a x delay) + na2 (a1 x delay) t pd (in out2 ) = t pd (in out0 ) + t pd (out0 out2 ) = 148.7 + 57 = 205.7 [ps] t pd (in out2 ) = t pd (in out0 ) + t pd (out0 out2 ) = 234.9 + 50 = 284.9 [ps] 3) delay in in out3 path = in1 (a x delay) + no2 (a1 x delay) t pd (in out3 ) = t pd (in out0 ) + t pd (out0 out3 ) = 148.7 + 59 = 204.7[ps] t pd (in out3 ) = t pd (in out0 ) + t pd (out0 out3 ) = 234.9 + 53 = 287.9 [ps] chapter 7 propagation delay and timing 170 epson embedded array S1X60000 series design guide (2) delay time of output cells the following describes the procedure for calculating the approximate amount of propagation delay time, using the circuits in figure 7-2 as an example. the output pin has a capacitance of 100 pf added external to the chip. table 7-3 lists various characteristic values of dual power supply output cells excerpted from the cell library. hob3 output pin cl=100pf a in pad figure 7-2 example circuit for calculation of the external cell propagation delay time table 7-3 delay characteristics of output cells (power supply hv dd = 3.3 v / lv dd = 2.5 v) input output delay characteristics (typ.) cell name pin fan-in [lu] pin fan-out [lu] from to parameter t 0 [ps] k [ps/10pf] t plh 2406 166.7 hob3 a 3.3 pad ? a pad t phl 1712 211.6 the delay time in the output cell hob3 under typ. conditions is calculated using equation 7-2, as shown below. here, the symbol ? ? denotes a rise, and the symbol ? ? denotes a fall. here, these refer to the rising and falling transitions at the pad for the output pin. t pd (in pad ) = t 0 ( ) + k ( ) 100 (pf) / 10 = 2406 + 166.7 100 (pf) / 10 = 4073 [ps] t pd (in pad ) = t 0 ( ) + k ( ) 100 (pf) / 10 = 1712 + 211.6 100 (pf) / 10 = 3828 [ps] 7.4 fluctuations in propagation delay time the t 0 and k values used to calculate the propagation delay time in input and internal cells (shown in equation 7-1) and in output cells (shown in equation 7-2) vary with the operating voltage and ambient temperature, as well as with process conditions. the ?S1X60000 series msi cell library? lists these values for max., typ., and max. conditions, respectively. these conditions are defined below for your reference. chapter 7 propagation delay and timing embedded array S1X60000 series epson 171 design guide min. condition: v dd = highest value, t a = lowest value, process = fast typ. condition: v dd = center value, t a = 25c, process = center value max. condition: v dd = lowest value, t a = highest value, process = slow the min. and max. condition propagation delays are important in confirming that circuit delays are within the desired range of specifications even when v dd , ta, or the process varies. coefficient m that represents a variation in min/max condition propagation delays can be calculated from typ conditions by using equation 7-3 below. m = mv mt mp ............ (equation 7-3) where, mv: coefficient of power supply voltage fluctuation mt: coefficient of ambient temperature fluctuation mp: coefficient of process fluctuation table 7-4 shows the standard coefficient of delay variations (m); figure 7-3 shows a graph indicating the mv and mt of msi cells. for other than the standard power supply voltage and ambient temperature ranges listed in table 7-4, please contact the sales division of epson. table 7-4 coefficient of delay variations (m) m value (t a = 0 to +70 c * * * * 1 ) m value (t a = -40 to +85 c * * * * 2 ) conditions min. typ. max. min. typ. max. hv dd = 3.3 v 0.3 v 0.72 1.00 1.39 0.68 1.00 1.44 v dd or lv dd = 2.5 v 0.2 v 0.72 1.00 1.45 0.68 1.00 1.53 input/output buffers v dd or lv dd = 2.0 v 0.2 v 0.69 1.00 1.53 0.65 1.00 1.56 v dd = 2.5 v 0.2 v 0.75 1.00 1.40 0.70 1.00 1.48 msi cells v dd = 2.0 v 0.2 v 0.72 1.00 1.48 0.68 1.00 1.56 *1: this temperature range is based on the assumption that t j = 0 to +85c. *2: this temperature range is based on the assumption that t j = -40 to +125c. chapter 7 propagation delay and timing 172 epson embedded array S1X60000 series design guide 1.2 1.1 1.0 0.9 0.8 t pd (ratio) 2.1 v dd (v) 2.3 2.5 2.7 2.9 t pd = 1.0 (v dd = 2.5v) t a = 25 c 1.2 1.1 1.0 0.9 0.8 t pd (ratio) -40 -20 -60 20 040 t a ( c) 60 80 100 120 140 v dd = 2.5v t pd = 1.0 (t a = 25 c) 1.2 1.1 1.0 0.9 0.8 t pd (ratio) 1.6 v dd (v) 1.8 2 2.2 2.4 t pd = 1.0 (v dd = 2.0v) t a = 25 c propagation delay vs. power supply voltage characteristics 1.2 1.1 1.0 0.9 0.8 t pd (ratio) -40 -20 -60 20 040 t a ( c) 60 80 100 120 140 v dd = 2.0v t pd = 1.0 (t a = 25 c) propagation delay vs. ambient temperature characteristics figure 7-3 delay characteristics of msi cells 7.5 setup and hold times of the flip-flop (ff) if the configured circuit is to operate properly with the desired logic, the timing of the signals applied to the sequential circuit of the ff or of an msi built with ffs is important. the setup and hold times of ffs are closely related to this signal timing. any data that is supplied after the setup time or that has changed state within the hold time cannot be written into the ff circuit properly. therefore, these setup and hold times must be taken into consideration in the timing design. (1) minimum pulse width this refers to the minimum length of time or the width from the leading to the trailing edge of an input pulse waveform in an ff or an msi built with ffs. if a pulse narrower than that value is applied to the input, it may not only have no effect as a signal, but may also cause the ff to operate erratically. there are the following three definitions of the minimum pulse width: ? minimum pulse width of a clock signal ? minimum pulse width of a set signal ? minimum pulse width of a reset signal chapter 7 propagation delay and timing embedded array S1X60000 series epson 173 design guide (2) setup time for data to be properly read into an ff or an msi built with ffs, the state of the data must be set before the active edge of the clock pulse changes. the time required for this is referred to as the ?setup time.? (3) hold time for data to be properly read into an ff or an msi built with ffs, the state of the data must be maintained for some time after the active edge of the clock pulse is entered. the time required for this is referred to as the ?hold time.? (4) release time (setup) a finite length of time must elapse before the clock pulse can change state after the state of the set/reset input is released in an ff or an msi built with ffs. this time is referred to as the ?release time (setup).? (5) removal time (hold) the state of the set/reset input must be maintained for some time after the clock pulse is entered in an ff or an msi built with ffs. this time is referred to as the ?removal time (hold).? (6) set/reset setup time (recovery) a finite length of time must elapse before the reset input can be driven high after the state of the set input is released in an ff or an msi built with ffs. this time is referred to as the ?set/reset setup time.? (7) set/reset hold time (recovery) the signal state must be maintained for some time before the set signal is driven high after the reset signal is driven high in an ff or an msi built with ffs. this time is referred to as the ?set/reset hold time.? for details regarding the timing error message during the simulation, refer to the manual of each tool. set data clock reset q xq d c s r q xq figure 7-4 dfsr chapter 7 propagation delay and timing 174 epson embedded array S1X60000 series design guide pulse width clock data removal release (setup) set setup hold (hold) (reset) set (reset) pulse width pulse width figure 7-5 timing waveform 1 (for definitions (1) to (5)) reset recovery (setup) set recovery (hold) set figure 7-6 timing waveform 2 (for definitions (6) to (7)) the setup/hold times of ffs in the S1X60000 series are listed in the ?S1X60000 series msi cell library? in the form shown in table 7-1. when actually using the S1X60000 series, please refer to the characteristics of each cell. chapter 8 estimating power consumption embedded array S1X60000 series epson 175 design guide chapter 8 estimating power consumption virtually no current flows through the chip of a cmos lsi when it is not in operation. however, during operation it consumes an amount of power corresponding to its operating frequency. the greater the power consumption, the higher the lsi chip temperature. an excessively high chip temperature adversely affects lsi quality. therefore, the power consumption of lsi chips must be calculated to verify whether it is within the range of the chip?s permissible power consumption. this chapter describes the procedure for calculating the power consumption of all chips in the S1X60000 series of products. 8.1 calculation of power consumption the power consumption of cmos circuits generally depends on the circuit?s operating frequency, load capacitance, and power supply voltage (this does not include special products such as analog circuits in which a steady state current flows in the chip). to calculate the power consumption of the entire chip, first find the power consumption of each block of the internal circuit, and then find the sum total for all blocks of the internal circuit. next, find the power consumption of the input and output buffers. the sum total of these is the total amount of power consumption to be obtained. the total amount of power consumption, p total , is calculated using the equation below. p total = p int + p i + p o where, p int : power consumption of the internal circuit p i : power consumption of the input buffers p o : power consumption of the output buffers 8.1.1 internal cells (p int ) the power consumption of internal cells varies with the gate counts used, efficiency of cell usage, operating clock frequency, and percentage of cells operating with that clock frequency, and is calculated using the equation below. p int = = k i 1 {(nb u) fi spi kpint} [w] where, nb : total bc counts of the circuit u : efficiency of cell usage fi : operating clock frequency of i?th cell [mhz] spi : ratio of bcs to all cells operating with clock frequency fi [mhz] (although this ratio varies with the content of each system, it may generally be considered to be in the range of 20% to 30%.) kpint : power consumption per bc (listed in table 8-1) table 8-1 kpint per bc of the S1X60000 series v dd (typ) kpi v dd = 2.5 v, lv dd = 2.5 v 0.18 w / mhz v dd = 2.0 v, lv dd = 2.0 v 0.11 w / mhz chapter 8 estimating power consumption 176 epson embedded array S1X60000 series design guide 2.1 v dd (v) i op (ratio) 2.3 2.5 2.7 2.9 1.4 1.2 1.0 0.8 0.6 0.4 t a = 25 c i op =1.0 (v dd = 2.5v) figure 8-1 1.6 v dd (v) i op (ratio) 1.8 2 2.2 2.4 1.4 1.2 1.0 0.8 0.6 0.4 t a = 25 c c i op = 1.0 (v dd = 2.0v) figure 8-2 8.1.2 input buffers (p i ) the power consumption of input buffers is obtained as the sum total of the frequencies of the input signals supplied to the respective buffers, f [mhz], multiplied by kpi [ w/mhz]. p i = = k i 1 (kpi fi) [w] where, fi : operating frequency of i?th input buffer [mhz] kpi : voltage coefficient of the input buffer (see table 8-2) table 8-2 kpi for input cells in the S1X60000 series v dd (typ) kpi hv dd = 3.3 v 3.8 w / mhz v dd = 2.5 v, lv dd = 2.5 v 2.6 w / mhz v dd = 2.0 v, lv dd = 2.0 v 1.6 w / mhz 8.1.3 output buffers (p o ) the power consumption of output buffers differs between dc load (e.g., resistive load or when connected to ttl devices) and ac load (e.g., capacitive load or when connected to cmos devices). if the dc power consumption and ac power consumption are assumed to be p dc and p ac , respectively, then the power consumption of the output buffers to be obtained, p o , is expressed by the equation below. p o = p ac + p dc 8.1.3.1 ac power consumption (p ac ) with an ac load, the power consumption of the output buffers can be roughly calculated using the equation below. p ac = = k i 1 {fi c l (v dd ) 2 } where, fi : operating frequency of the output buffer [hz] c l : output load capacitance [f] v dd : power supply voltage [v] chapter 8 estimating power consumption embedded array S1X60000 series epson 177 design guide 8.1.3.2 dc power consumption (p dc ) with a dc load, the power consumption of the output buffers can be roughly calculated using the equation below. p dc = p dch + p dcl where, p dch = |i oh | (v dd * - v oh ) p dcl = i ol v ol here, the ratio of p dch to p dcl is determined by the duty cycle of the output signal. t t 1 t 2 figure 8-3 example of a duty cycle using figure 8-3 as an example, we find duty h = (t 1 + t 2 ) / t duty l = (t - t 1 - t 2 ) / t from the above, p dc = p dch + p dcl = = k i 1 { (v dd * - v oh i) i oh i duty h} + = k i 1 [v ol i i ol i duty l] * for dual power supplies, v dd represents hv dd or lv dd . 8.2 limitations on power consumption the chip temperature of lsis increases according to their power consumption. when encapsulated in a package, the lsi?s chip temperature may be calculated from its ambient temperature, t a , the thermal resistance of the package, j-a, and the power dissipation of the lsi, pd. chip temperature (t j ) = t a + (pd j-a) [ c] when used under normal conditions, make sure the chip temperature (t j ) is 125 c or less. see table 8-3 for the thermal resistance of each type of package. the thermal resistance values shown in this table vary significantly depending on how the chip is mounted on the board and whether it is forcibly air cooled. chapter 8 estimating power consumption 178 epson embedded array S1X60000 series design guide table 8-3 thermal resistance of each type of package (suspended singly) h2qfp8 qfp5 qfp5 qfp8 qfp8 qfp12 qfp13 qfp14 qfp15 tqfp14 tqfp14 tqfp15 pin counts 100 128 128 208 48 64 80 100 80 100 100 110( c/w) 110 65 45 230 170 110 115 100 100 110 alloy42 j-a j-a j-a 0 m/sec 1 m/sec 2 m/sec 3 m/sec 75 75 ? ? ? ? ? 50 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 60 60 45 55 55 35 qfp20 144 85 70 50 40 qfp5 qfp5 qfp5 qfp8 qfp8 qfp10 qfp12 qfp13 qfp14 qfp15 qfp20 qfp21 qfp21 qfp22 qfp22 qfp23 qfp23 tqfp12 tqfp13 tqfp15 tqfp24 hqfp8 h2qfp23 h3qfp15 80 100 128 160 256 304 48 64 80 100 184 176 216 208 256 184 240 48 64 128 144 160 240 128 85 ( c/w) 80 80 45 50 35 175 130 110 90 65 55 55 45 45 40 40 165 140 105 80 32 30 85 cu-l/f 0 m/sec 1 m/sec 2 m/sec 3 m/sec 55 55 55 32 ? 20 120 80 ? ? ? ? ? 35 35 ? ? ? ? ? ? 19 ? ? 45 35 35 25 16 90 55 25 25 12 40 30 30 23 80 50 23 23 10 hqfp5 128 60 ? 208 34 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? pbga pbga pbga 225 256 388 72 ( c/w) 53 45 pbga 46 33 ? 37 25 ? ? ? ? j-a j-a j-a j-a j-a j-a j-a j-a j-a cflga424 cflga307 cflga239 cflga152 cflga104 customer?s board size 75 mm 50 mm 30 mm 75 mm 50 mm 30 mm 75 mm 50 mm 30 mm 75 mm 50 mm 30 mm 75 mm 50 mm 30 mm cflga (mounted on the board, free of wind) 3.82 mm x 3.82 mm 5.73 mm x 5.73 mm chip size 44.0 ( c/w) 46.9 61.1 44.0 47.1 61.7 44.0 47.3 62.2 44.8 48.8 63.3 45.5 50.3 64.3 32.9 36.4 50.1 33.1 37.4 51.5 33.1 38.3 52.9 34.4 39.7 53.9 35.6 41.1 54.9 24.6 27.8 42.1 24.9 28.5 43.1 25.1 29.2 43.9 ? ? ? ? ? ? 9.55 mm x 9.55 mm package type package type pin counts package type 0 m/sec 1 m/sec 2 m/sec 3 m/sec pin counts package type chapter 9 circuit design embedded array S1X60000 series epson 179 design guide chapter 9 circuit design 9.1 basic circuit configuration 9.1.1 inserting input/output buffers signals outside and inside an lsi can only be exchanged via input/output buffers. always be sure to insert input or output buffers between the external pins and the internal cells of an lsi. this is necessary because cmos lsis are extremely susceptible to static electricity, and the input/output buffers contain a circuit that protects them against static electricity. 9.1.2 limitations on logic gate output load cmos circuits are such that, as the load capacitance of the output increases, so does the propagation delay time of signals (t pd ). at the same time, the rise and fall times of signal waveforms (t slew ) increase. if logic gates have an excessively large output load capacitance, signal delay may concentrate at a specific circuit node, thereby limiting the operating speed or deteriorating the simulation accuracy of the logic gate?s propagation delay time, which in turn could cause the logic gate to operate erratically. furthermore, because the change period of signals is extended, the logic gate may become susceptible to noise. to ensure that logic gates have an appropriate load in the circuit design stage, limitations known as ?fan-out? limits are provided to limit the load that can be connected to the logic gate. the input pins of logic gates each have a specific input capacitance defined as the ?fan-in,? which is a relative quantity referenced to the input capacitance of inverter cell (in1) =1. on the other hand, fan-out limits are expressed as the sum total of fan-in counts, which can be connected to the output pin of each logic gate. in the design of your circuit, make sure the sum total of the fan-in counts connected to the output pin of each logic gate will not exceed the fan-out limits for that output pin. for logic gates such as clock lines that operate at high speed (operating frequency of 60 mhz or higher), make sure the load on their output pins is approximately half the ordinary fan-out limits. the output-pin load capacitance of logic gates in an actual lsi consists of the input capacitance of gates in the next stage plus the wiring capacitance of signals. because the exact wiring capacitance is determined through placement and routing in the circuit, a large load capacitance may be applied to specific nodes during placement and routing, depending on how the work is performed. the load condition at each circuit node can be verified from the output results of t slew . if the output results suggest that the load condition exceeds the rated value, customers may be requested to correct the circuit in order to suppress the load to within the limits. to suppress increases in load capacitance after placement and routing work has been performed, minimize circuit branches at a single node or, if branching, use buffers with large fan-out. 9.1.3 wired logic forbidden because the S1X60000 series cells use cmos transistors, they cannot be configured with wired logic as in bipolar transistors. as a result, the output pins of cells cannot be connected together, as shown in figure 9-1. only in the bus circuit configuration is it possible to connect the output pins together. chapter 9 circuit design 180 epson embedded array S1X60000 series design guide figure 9-1 examples of forbidden wired logic 9.1.4 synchronized design recommended for the logic circuit design, we recommend synchronized design in which all registers are basically clocked from a common timing signal source. synchronized design provides numerous advantages. for example, it is suitable for high speed circuits because register to register operations can easily be timed. it can make use of various eda tools, such as clock tree synthesis, dft, and sta. in addition, because it does not depend on technology-inherent characteristics, circuits can easily be reused. ideally speaking, synchronized circuits have the following characteristics: 1. all registers in the circuit operate with either the rising or falling edge of a single clock signal. 2. no feedback loops are based on a combinational circuit (see figure 9-2). 3. no pulse generator circuits that make use of a circuit delay are included (see figure 9-3). 4. other than the system reset, no asynchronous resets are used (this also applies to asynchronous sets). although in reality it may be difficult to design a circuit in which registers are clocked by a single clock signal, we recommend using as few clock signals as possible. the greater the number of clock signals used and the greater the complexity of the mutual relationships between them, the more time is required for circuit design, including the operation of said eda tools, and the less likely it is to obtain satisfactory output results. figure 9-2 example of a feedback loop d c r q xc figure 9-3 example of a delay-based pulse-generator circuit chapter 9 circuit design embedded array S1X60000 series epson 181 design guide 9.2 use of differentiating circuits forbidden the propagation delay time of each element in an lsi, t pd , varies depending on the working environment (e.g., voltage and temperature) and manufacturing conditions. for this reason, care must be taken in the use of differentiating circuits that make use of the difference in relative t pd times(see figure 9-4), as a sufficient pulse width may not be obtained depending on the working environment and manufacturing conditions, causing the circuit to operate erratically. when a differentiating circuit is needed, avoid using the circuit shown in figure 9-4 and, instead, use a circuit built with ffs like the one shown in figure 9-5. figure 9-4 example of a bad differentiating circuit clk ck d q xq ck d q xq figure 9-5 example of a differentiating circuit built with ffs chapter 9 circuit design 182 epson embedded array S1X60000 series design guide 9.3 clock tree synthesis 9.3.1 overview clock tree synthesis clock tree synthesis clock tree synthesis clock tree synthesis is a service that allows a tree of buffers to be inserted automatically in order to optimize the skew and delay values of clock lines. when circuits are designed by customers, they often insert clock trees as a means of adjusting the fan-out of clock lines or for other purposes. in such a case, because clock trees are placed and routed so as to be suitable for the placement and routing tool, the clock skew and wiring delay tend to increase. therefore, we recommend that buffers not be inserted in clock lines for fan-out adjustment purposes; instead, we recommend that you receive this service from epson. for circuits that also contain gated cells (simple gates) (simple gates) (simple gates) (simple gates) in clock lines, clock tree synthesis helps optimize the skew and delay values of clock lines. before clock tree synthesis can be applied, customers are requested to insert dedicated buffers or dedicated gated cells in clock lines for the following three purposes: (1) to determine the location at which clock tree synthesis is applied (2) to perform temporary wiring level simulation (pre-simulation) using the predicted delay values of clock trees to be inserted (3) to back annotate after replacing the inserted clock trees with delay information, in order to perform precise post-simulation chapter 9 circuit design embedded array S1X60000 series epson 183 design guide 9.3.2 design flow p & r clock tree synthesis post-p&r netlist * sdf post-simulation post-simulation result post-simulation result confirmed ok ng circuit change circuit verification netlist after circuit change pin layout table or ppd eco (enginnering change order) post-p&r netlist * sign-off clock tree synthesis checksheet initial netlist pin layout table or ppd customer epson (eco is a method for performing placement and routing only in locations where the circuit has been changed.) [ [ [ [notes notes notes notes] ] ] ] ? the post-p&r netlist contains buffers that have been added in clock tree synthesis. ? post-simulation uses the netlist and sdf, which contain the buffers that have been added in clock tree synthesis. ? if the result of post-simulation is no good (ng), correct the post-p&r netlist. if the initial netlist has been corrected, p&r must be reexecuted. ? if circuit changes are made to the clock net part (dedicated buffer, dedicated gated cell, and def), p&r must basically be reexecuted. if it is necessary to change the clock net part, please consult with epson. chapter 9 circuit design 184 epson embedded array S1X60000 series design guide 9.3.3 applying clock tree synthesis refer to table 9-2, ?dedicated buffers,? for the selection of clock tree synthesis only buffers, and to table 9-3, ?cell names of dedicated gating cells,? for the selection of clock tree synthesis only gating cells. in addition, after gaining an understanding of the limitations and notes in section 9.3.4, refer to reference circuit diagram 1 when inserting the dedicated buffers or dedicated gating cells that you?ve selected. for logic synthesis based design, because the dedicated buffers and dedicated gating cells cannot be automatically inserted, use direct language descriptions. in such a case, to ensure that the clock line in which dedicated buffers or dedicated gating cells have been inserted will not have other buffers or the like synthesized in it, execute the following command in the design compiler: set_dont_touch_network clock_ name table 9-1 criteria for appropriate skew values standard fan-out counts without gating cells with gating cells 0 to 500 200 ps 300 ps 500 to 3000 250 ps 400 ps 3000 to 10000 300 ps 500 ps 10000 or more 350 ps 600 ps notes: notes: notes: notes: ? the criteria for appropriate skew values change according to the circuit size, wiring congestion, and number of clock lines. ? make sure the number of gated cells inserted is not more than 20, and that the number of stages does not exceed one. ? the above criteria for appropriate skew values when gating cells are included apply to cases in which not more than 20 gating cells are inserted and there are not more than one stage. ? if more gating cells are inserted so as to exceed the limit of three stages, skew-derived timing errors may occur during post-simulation. to avoid delays in development schedules, try to minimize the number of gating cells used. table 9-2 dedicated buffers S1X60000 series cell name t 0 max (ns) standard fan-out counts crbf2 2.00 0 to 500 crbf3 3.00 500 to 3000 crbf4 4.00 3000 to 10000 crbf5 5.00 10000 or more crbf6 6.00 crbf7 7.00 crbf8 8.00 notes notes notes notes: : : : ? the pre-simulation time k value (delay due to fan-out) for these cells is set to 0. chapter 9 circuit design embedded array S1X60000 series epson 185 design guide ? the fan-out counts for these cells are set to infinite. ? the delay values relative to the fan-out counts fluctuate depending on the design size and usage efficiency. therefore, use them for reference purposes only in the design of a circuit. table 9-3 cell names of dedicated gating cells circuit configuration (function) cell name and cad2v or cor2v 2-1 selector cao24av nand cna2v nor cno2v 2-1 selector can24av inverter cgin4 latch-based and clad2v latch-based or clor2v latch-based and with test pin clpsad2v latch-based or with test pin clpsor2v the gating cells available include latch-based gating cells. when using this type of cell, there is no propagation of switching glitches in the clock wiring. consequently, the clock signal is stabilized. refer to the ?S1X60000 series msi cell library? for the functional configuration of latch-based gating cells. notes notes notes notes: : : : ? the pre-simulation time delay value (t 0 ) for these cells is set to 0. ? the pre-simulation time k value (delay values due to fan-out) for these cells is set to 0. ? the fan-out counts for these cells are set to infinite. chapter 9 circuit design 186 epson embedded array S1X60000 series design guide 9.3.4 limitations and notes ? when clock tree synthesis is applied, the number of gates in the circuit for which it is applied increases by approximately 10% to 30%. ? if a large number of gating cells are inserted, skew derived timing errors may occur during post-simulation. to avoid causing delays in development schedules, try to minimize the number of gating cells used. ? the dedicated buffers and dedicated gating cells can only be used in clock tree synthesis, and cannot be used for any other purposes. ? clock tree synthesis can also be used for data lines and control, or for other signal lines. however, applying clock tree synthesis to a large number of nets results in an increase in the skew or delay. therefore, make sure clock tree synthesis is not applied to more than 10 nets, and that it is applied only to critical nets with large fan-out. ? if clock tree synthesis is applied to nets with small fan-out, the delay or skew may increase. make sure clock tree synthesis is applied only to nets with a fan-out of several tens or more. ? if the clock line contains any cell other than the dedicated gating cells, skew may occur during pre-simulation. therefore, make sure only the dedicated gating cells are inserted in the clock line. ? always be sure to use the dedicated gating cells in combination with the dedicated buffers. note that if only the dedicated gating cells are used inadvertently, the skew and delay values cannot be optimized. ? as the number of dedicated gating cells inserted in one clock net increases, so do the skew and delay values. therefore, limit the number of dedicated gating cells inserted in one clock net to a maximum of 20. ? as the number of stages comprised of dedicated gating cells increases, so do the skew and delay values. therefore, limit the number of stages comprised of dedicated gating cells to a maximum of one. ? skew adjustment, by default, is applied to cells such as dffs and latch cells that contain clock pins. if skew adjustment is required for other than dffs and latch cells, i.e., cells without clock pins, please contact epson. ? if the net for which clock tree synthesis is used is connected to megacell input pins, skew adjustment is not applied beyond the megacell input pins. ? do not insert the dedicated buffers in two or more stages. note that if the clock net contains dedicated buffers, the skew and delay cannot be optimized. chapter 9 circuit design embedded array S1X60000 series epson 187 design guide 9.3.5 clock tree synthesis checksheet when applying clock tree synthesis, customers are requested to provide epson with the following information. your cooperation is appreciated. z target skew value and target delay value instance name of crbf* target skew value (max.) (sim condition: max.) target delay value (min./max.) (sim condition: max.) notes: ? the target values are used for reference purposes only when they are applied to clock tree synthesis, and cannot be guaranteed to be satisfied. 1. is the number of clock lines within 10? yes y no 2. does the clock net contain dedicated gating cells? yes y no if you answered yes to both of the above two questions, please answer questions 3 to 8 below. 3. is the number of dedicated gating cells included in each clock net within 20? yes y no 4. is the number of stages comprised of dedicated gating cells within 1? yes y no 5. does the clock net contain dedicated buffers? yes y no 6. does the clock net contain any cell other than the dedicated gating cells? yes y no if yes, write the cell name below. [notes] ? if 3-input ands are handled as special gating cells, for example, the 3-input ands in all clock lines are handled as special gating cells. ? dffs and latches cannot be handled as special gating cells. 7. do you want skew adjustment to be applied to other than dffs and latches? yes y no if yes, specify the cell names and input-pin names. cell name: pin name: cell name: pin name: [notes] ? if you specify inverters to be skew-adjusted, for example, the inverter cells in all clock lines are adjusted for skew. 8. does any circuit configuration like reference circuit diagram 2 yes y no included herein exist? [notes] ? the clock net for both dffs, one in part a and one in part b of the diagram, cannot be optimized for skew. if the dffs in both parts a and b must be adjusted for skew, add dummy cells ?cao24av? as shown in reference circuit diagram 2. 9. does any circuit configuration like reference circuit diagram 3 yes y no included herein exist? [notes] ? the dff in part a of the diagram is driven from both clock roots a and b. the dff in part a cannot be adjusted for skew in both clock roots a and b. the ?crbf? for clock root b in reference circuit diagram 3 must be deleted. chapter 9 circuit design 188 epson embedded array S1X60000 series design guide 9.3.6 attached materials 9.3.6.1 concept of the implementation of clock tree synthesis d c q xq r dfr v cad2v crbf2 clock root d c q xq r dfr d c q xq r dfr d c q xq r dfr before clock tree synthesis clock tree synthesis optimizes the skew value for the thick-lined parts. d c q xq r dfr v cad2v crbf2 clock root d c q xq r dfr d c q xq r dfr d c q xq r dfr a fter clock tree synthesis reference circuit diagram 1 when clock tree synthesis is applied, buffers are inserted within the dotted circles of the above circuit. chapter 9 circuit design embedded array S1X60000 series epson 189 design guide 9.3.6.2 example of handling of a problem circuit?1 d c q xq r dfr v cao24av crbf2 clock root a d c q xq r dfr d c q xq r dfr d c q xq r dfr clock root b crbf2 original circuit clock tree synthesis cannot be executed for the dffs connected in the thick-lined part, as they are driven from both clock roots a and b. d c q xq r dfr v cao24av crbf2 clock root a d c q xq r dfr d c q xq r dfr d c q xq r dfr clock root b crbf2 modified circuit pdw v cao24av dummy cell reference circuit diagram 2 the dffs within the dotted circle of the original circuit are driven from both clock roots a and b. clock tree synthesis cannot be applied to any circuit in this manner. in the case of a circuit such as that in this example, insert a dummy cell ?cao24av,? as shown in the corrected circuit. in such a case, clock tree synthesis optimizes the skew value of the thick-lined part of the circuit. chapter 9 circuit design 190 epson embedded array S1X60000 series design guide 9.3.6.3 example of handling of a problem circuit?2 d c q xq r dfr v cao24av crbf2 clock root a d c q xq r dfr d c q xq r dfr d c q xq r dfr clock root b crbf2 reference circuit diagram 3 in the above circuit, the dffs within the dotted circle are driven from both clock roots a and b. clock tree synthesis cannot be applied to any circuit in this manner. in the case of a circuit such as that in this example, delete the cell ?crbf2? that is inserted in clock root b. 9.3.6.4 problem circuit 1 d c q xq r dfr v cad2v crbf2 d c q xq r dfr d c q xq r dfr d c q xq r dfr reference circuit diagram 4 in the above circuit, the cell ?crbf2? is inserted in the stage following that of the cad2v cell, which comprises multiple dedicated buffer stages. the crbf2 cell in the stage following that of the cad2v cell is unnecessary; therefore, it should be deleted. chapter 9 circuit design embedded array S1X60000 series epson 191 design guide 9.3.6.5 problem circuit 2 d c q xq r dfr v cao24av crbf2 clock root a d c q xq r dfr d c q xq r dfr d c q xq r dfr clock root b crbf2 reference circuit diagram 5 in the above circuit, the dffs within the dotted circle are driven from both clock roots a and b. clock tree synthesis cannot be applied to any circuit in this manner. in the case of a circuit such as that in this example, delete the cell ?crbf2? that is inserted in clock root b. 9.3.6.6 problem circuit 3 d c q xq r dfr v cad2v crbf2 d c q xq r dfr d c q xq r dfr d c q xq r dfr crbf2 reference circuit diagram 6 in the above circuit, the cell ?crbf2? is inserted in the stage following that of the cad2v cell, which comprises multiple dedicated-buffer stages. the crbf2 cell in the stage following that of the cad2v cell is unnecessary; therefore, it should be deleted. chapter 9 circuit design 192 epson embedded array S1X60000 series design guide 9.4 designing fast operating circuits for fast operating circuits (operating frequency of 60 mhz or more), due to the reduced per-cycle time, the operable delay time has a small margin with respect to the propagation delay time. therefore, devise appropriate countermeasures to minimize propagation delays by taking the precautions described below into consideration in the design of a circuit. chapter 9 circuit design embedded array S1X60000 series epson 193 design guide 9.5 metastable state if the input signals for flip-flops or latch cells are in violation of timing specifications (such as the clock and data setup and hold times, or the clock and set/reset release or removable times), the output signals of the flip-flops or latch cells may be oscillating or at an intermediate voltage level, neither high nor low, for a certain period of time. the instable state of output signals as in this case is referred to as the ?metastable? state. the metastable state ends after the elapse of a certain length of time, and the output is fixed to the high or low level. however, because this fixed output level does not depend on the level of the input data, the output is indeterminate. if the setup/hold or release/removal timing specification cannot be met, be sure to incorporate corrective measures in circuit design in order to ensure that such an instable state will not propagate to the entire circuit. for the S1X60000 series, the duration of the metastable time in cases in which the designated values of the setup/hold or release/removal times cannot be satisfied is defined as a standard value, as follows: metastable time = t pd 6 where, t pd : delay time from the active edge of the clock or set/reset signal for a flip-flop or latch cell, until its output changes. because delay values in such a metastable state are not taken into consideration during logic simulation, always make sure a circuit being designed satisfies the timing specification. cxq dq df data clock q xq hold setup clock data tpd expected output value: q output: q (metastable state) metastable state indeterminate state figure 9-6 metastable state of the df chapter 9 circuit design 194 epson embedded array S1X60000 series design guide 9.6 configuration of the internal bus the bus circuit is configured using 3-state logic circuits; therefore, one of the outputs connected to the bus is driven active (while the other output is placed in the high impedance state) through manipulation of the control signals for the bus, allowing one transmission signal line to be time shared. the following describes the precautions to be taken when configuring an internal bus circuit using internal tri-state buffers. ? bus cells can only be used in a bus circuit, and not in any other circuit (see table 9-4 for the bus cells in the S1X60000 series). ? when configuring a bus circuit, add the bus latch cell *blt.* ? of the bus cells connected to one bus, only one output can be in an active state (logic 0 or 1), and all other bus-cell outputs must be placed in the high impedance (hi-z) state. *1 ? the number of bus cells that can be connected to one bus must be within the fan-out limits. *2 ? the bus circuit tends to have a large propagation delay time due to fan-out, making it unsuitable for high speed operation. *2 ? the data retained by a bus latch cell can only be used to prevent the bus from floating, and cannot be used as a logic signal. *3 ? when creating test patterns, exercise caution to ensure that the initial state of the bus can be determined easily. *4 ? make sure control signals for the bus change state only once within one cycle. notes) *1: if two or more of the bus cells connected to one bus are in an active state (logic 0 or 1) at the same time, the output voltage may not only become instable, but may also cause a steady current to flow between v dd and gnd. this limitation should always be taken into consideration. *2: if an excessively large load is placed on the internal bus, the signal rise and fall times increase due to the increased wiring length and increased number of driven cells. this may result in a difference between the delay time in logic simulation and the delay time in the actual device. *3: even though all of the bus cells connected to one bus enter a high impedance (hi-z) state, data is retained by a bus latch cell. however, the latch?s holding capability is restrained so as not to adversely affect operation. do not use the retained output data as valid data. *4: configure the bus so as to improve its testability by, for example, adding test pins in order to increase the bus? controllability. chapter 9 circuit design embedded array S1X60000 series epson 195 design guide table 9-4 bus cells available in the S1X60000 series celle name cell type 1 bit 4 bit 8 bit bus latches blt 1 blt 4 blt 8 bus driver tsb, tsb 4, tsb8, tsbp t 244h t 244 inverting bus driver tsv, tsv 4, tsv8, tsvp t 240h t 240 transparent laches with reset and 3-state output ? t 373h t 373 d-flip flops with reset and 3-state output ? t 374h t 374 1-bit ram rm 1 ? ? tsb tsb blt1 in 1 na2 figure 9-7 typical configuration of a bus cell circuit chapter 9 circuit design 196 epson embedded array S1X60000 series design guide 9.7 preventing contention with external buses in a system built using gate arrays and other lsis, if they are connected in a bus configuration, take appropriate measures, in addition to the precautions described in section 9.6, ?configuration of the internal bus,? by inserting pull-up/pull-down resistors, for example. to prevent external buses from floating, input/output cells with pull-up/pull-down resistors or input/output cells with a bus hold function (*) may be used. note that if appropriate measures are not taken prior to use, due to the indeterminate input level, functional failure or increased input leakage current may be encountered. *: bus hold circuit input/output buffers with a bus hold function are available in the S1X60000 series. to prevent the output pins or bi-directional pins from entering a high impedance state, these buffers hold the data at the output pins intact. however, because the bus hold circuit?s holding capability is restrained so as not to adversely affect normal operation, do not use the retained output data as valid data. in the event any data is supplied from the outside, the retained data may change state easily. for details on the bus hold circuit?s output retention current, refer to the electrical characteristics specified in this manual. tb1ht a e ta for test output signal output te ts enable (a) output buffer (b) bi-directional buffer bc1ht a e ta for test output signal bi-directional te ts enable input signal figure 9-8 example of a bus hold circuit symbol chapter 9 circuit design embedded array S1X60000 series epson 197 design guide 9.8 hazard protection circuits or decoder cells comprised of a combination of nand and nor gates tend to generate very short pulses, depending on the difference in propagation delays between those gates. these short pulses are known as a ?hazard.? if such a hazard enters the clock or reset pins of an ff (flip-flop), it causes the ff to operate erratically. for circuits in which such a hazard is likely to occur, therefore, protective measures must be taken by, for example, devising a circuit configuration that prevents the hazard from propagating or using a decoder circuit provided with an ?enable? pin. d c q d c q d c q d c q d c q d c q figure 9-9 example of hazard protection chapter 9 circuit design 198 epson embedded array S1X60000 series design guide 9.9 oscillation circuits 9.9.1 configuration of oscillation circuits two types of dedicated oscillation cells are used to configure an oscillation circuit: one for a crystal oscillation, and one for an cr oscillation. furthermore, there are two types of cells for crystal oscillation use, a steadily oscillating type and an intermittently oscillating type, and either type can be placed in an internal cell area or an i/o cell area. the oscillation circuit may be configured in various ways, depending on which type of oscillation cell is used, as shown below. g x d xlin xlot rf x?tal rd cg cd inside the ic oscillation cell for steady oscillation g e x d xlin xlot rf x?tal rd cg cd oscillation cell inside the ic for intermittent oscillation figure 9-10 crystal oscillation circuit (internal cell type) rf x?tal rd cg cd inside the ic xlin oscillation cell g x pad for steady oscillation figure 9-11 crystal oscillation circuit ( i/o cell type) chapter 9 circuit design embedded array S1X60000 series epson 199 design guide g x r c xlin xlot xlo r c inside the ic oscillation cell figure 9-12 cr oscillation circuit chapter 9 circuit design 200 epson embedded array S1X60000 series design guide 9.9.2 notes regarding the use of oscillation circuits (1) pin layout ? the input/output pins of the oscillation circuit must be placed close to each other, and must be enclosed with the power supply pins (v dd , v ss ) at both ends. ? the input/output pins of the oscillation circuit must be placed away from other output pins. in particular, they must be separated from outputs that are in phase or are 180 degrees out of phase with the oscillation waveform. make sure these outputs are placed on the other side of the package, opposite the oscillation circuit. ? the input/output pins of the oscillation circuit must be placed away from other input pins such as a clock input, which operate at high speed. ? the input/output pins of the oscillation circuit must be placed as close to the center of one edge of the package as possible. ? when incorporating two or more oscillation circuits in the design, make sure those oscillation circuits are placed apart from each other in order to prevent interference. ? when using area array packages such as bga, consult the sales division of epson for the pin layout of the package. (2) test pattern generation for details on how to create test patterns for designs using an oscillation circuit, refer to section 11.5, ?notes regarding the use of oscillation circuits,? in chapter 11, ?test pattern generation.? (3) selecting oscillation cells the oscillation frequencies available with the oscillation cells are in the range of several tens of khz to tens of mhz. for more information, contact the sales division of epson. (4) setting external resistor and capacitor values the oscillation characteristics of an oscillation circuit depend on its constituent elements (ic, x?tal, rf, rd, cg, cd, and board). therefore, before determining the values of external rf, rd, cg, or cd, sufficiently evaluate those components while they are mounted on the actual board. in this way, attempt to select the most appropriate values for those components. (5) guaranteed level the oscillation characteristics of an oscillation circuit depend on its constituent elements (ic, x?tal, rf, rd, cg, cd, and board). therefore, epson cannot guarantee the oscillation performance and characteristics of oscillation circuits designed by customers. the oscillation characteristics of those oscillation circuits must be verified by customers themselves through sufficient evaluation using es samples. (6) oscillation circuit configuration in a dual power supply system the oscillation circuit in a dual power supply system can basically be configured in the same way as a single power supply system. in this configuration, the oscillation cells are connected to the lv dd power supply. for the input/output cells xlin and xlot used in this configuration, therefore, select those labeled ?xllin? and ?xllot?. moreover, when using 5 v tolerant i/o cells, please be sure to use xfllin and xfllot, respectively. chapter 9 circuit design embedded array S1X60000 series epson 201 design guide 9.10 restrictions and constraints on vhdl/verilog-hdl netlist the vhdl/verilog-hdl netlist to be interfaced to epson shall be a pure gate level netlist (not containing function and description of operation). the restrictions and constraints in developing epson asic using vhdl/verilog-xl are as follows. 9.10.1 common restrictions and constraints (1) names of external pin (i/o pin) ? use only upper case letters. ? number of characters: 2 to 32 ? bus description is prohibited. ? usable characters: alphanumeric characters and ?_.? use an alphabetical letter at the head. ? examples of prohibited character strings: 2 input: a digit is at the head. \2input: ?\? is at the head. inputa: lower case letters are included. _inputa: ?_? is at the head. ina[3:0]: a bus is used for the name of the external pin. ina[3]: a bus is used for the name of the external pin. (2) names of internal pin (including bus net names) upper and lower case letters can be used in combination, except the following. combinations of the same words expressed in upper and lower case letters, such as ?_reset_? and ?_reset_.? ? number of characters: 2 to 32 ? usable characters: alphanumeric characters, ?_?, ?_[]_? (verilog bus blanket), and ?_()_? (vhdl bus blanket) with an alphabetical letter at the head. (3) module names in systems, module names are discriminated between the uppercase and lowercase. in design rules, however, mixed use of uppercase and lowercase module names is prohibited. example: mixed use of ?and? and ?and? because cells are case-sensitive, be careful about upper and lower case when you enter module names. (4) bus description is prohibited at the most significant place of the module. examples: data [0:3], data [3], and data [2] are prohibited. data0, data1, and data2 are all allowed. chapter 9 circuit design 202 epson embedded array S1X60000 series design guide (5) you can use i/o cells of the same library series, but cannot combine those of different series. (6) it is not possible to describe operations in behaviors, in rtl, or in the c language. such descriptions existing in the netlist are invalid. (7) precision of the time scale of the library of each series is 1ps. 9.10.2 restrictions and constraints for verilog netlist (1) descriptions using the functions ?assign? and ?tran? are prohibited in the gate level verilog netlist. (2) descriptions of connection with cell pin names are recommended in the verilog netlist. examples: possible: in2 inst_1 (.a(inst_2),.x(inst_3)) not possible: in2 inst_1(net1, net2) (3) you cannot use the verilog command ?force? as a description of flip-flop operation. example: force logic .singal = 0 (4) the time scale description is added at the head of the gate-level netlist generated by the synopsys design compiler. set it at the value described in the epson verilog library. time scale of each series is 1ps. example: `timescale 1ps/1ps (5) epson prohibits combination of a bus single port name and a name that includes ?_\_?, such as the following, in the same module. input a [0] wire \a [0] (6) the following letter strings are reserved for verilog, which cannot be used as a user-defined name. always and assign begin buf bufif0 bufif1 case design default defparam disable else end endcase endfunction endmodule endtask event for force forever fork function highz0 highz1 if initial inout input integer join large medium module nand negedge nor not notif0 notif1 or output parameter posedge pull0 pull1 reg release repeat scalared small specify strong0 strong1 supply0 supply1 task time tri tri0 tri1 trinand trior trireg vectored wait wand weak0 weak1 while wire wor xor xnor chapter 9 circuit design embedded array S1X60000 series epson 203 design guide 9.10.3 restrictions and constraints on vhdl netlist (1) in addition to the constraints in 9.10.1 (1), the following letter strings are also prohibited. because the simulation is performed using textio package, the name of functions used in textio package cannot be defined for users. inputa_: ?_? is used at the end. input_ _a: ?_? is used twice or more in succession. read: used in the system. write: used in the system. (2) the following letter strings are reserved for vhdl, which cannot be used as a user-defined name. abs access after alias all and architecture array assert attribute begin block body buffer bus case component configuration constant disconnect downto else elsif end entity exit file for function generate generic guarded if in inout is label library linkage loop map mod nand new next nor not null of on open or others out package port procedure process range record register rem report return select severity signal subtype then to transport type units until use variable wait when while with xor (3) to use epson utilities and tools, it is necessary to change the vhdl format into the verilog format. therefore, the letter strings reserved for verilog in 9.10.2 (6) are also prohibited. 9.10.4 description of oscillation cell and ac/dc test circuit cell l1tcir2 it is recommended that oscillation cells be described after being turned into instances, and that the dont_touch attribute be attached to the input and output nets by using the set_dont_touch command, in order to ensure that no buffers are inserted into the oscillation cells? external-pin connecting nets when synthesized. as ac/dc test circuit cell l1tcir2 are available as hard macros, it is recommended that they be entered in the form of gate descriptions, as shown in the examples below. ? example of verilog-hdl description ? l1osc1 inst1 (.g(gate_in), .d(drain_out), .x(clk_out) ); l1tcir2 inst2 (.tm0(i_net0), .tm1(i_net1), .tm2(i_net2), .tm3(i_net3), .tst(i_net4), .ms(ms), .td(td), .te(te), .ts(ts), .tac(tac) ); chapter 9 circuit design 204 epson embedded array S1X60000 series design guide ? example of vhdl description ? inst1 : l1osc1 port map (g ? gate_in, d ? drain_out, x ? clk_out); inst2 : l1tcir2 port map (tm0 ? i_net0, tm1 ? i_net1, tm2 ? i_net2, tm3 ? i_net3, tst ? i_net4, ms ? ms, td ? td, te ? te, ts ? ts, tac ? tac ); 9.10.5 clock buffer description when performing hierarchical design, please make sure that the clock root buffers are inserted in the upper layers (to the extent possible), so that gated cells will not have multiple linked stages. for clock root buffers and gated cells, it is recommended that gated cells be written directly in rtl description. when using epson gate libraries in rtl simulation, please make sure a sufficient input delay is allowed in the test patterns you create, as there will be some delay in the clock root buffers. ? verilog description ? module top (clk, reset, ....., ); input clk, reset, ... ; output out1, out2, ... ; libcy pad1 (.pad(clk), .x(iclk) ); l1crbf2 u0_l1crbf2 (.a(iclk), .x(wclk) ); . . clkgen u_clkgen (.clk(wclk), .aclk(aclk), .bclk(bclk) ...); aif u_aif (.aclk(aclk), .....); bif u_bif (.bclk(bclk), .....); endmodule module clkgen (clk, aclk, bclk); input clk; output aclk, bclk ; licad2x4 gatedclkand0 (.a1(clk), .a2(a_gate),.x(aclk) ); licad2x4 gatedclkand1 (.a1(clk), .a2(b_gate),.x(bclk) ); ... endmodule chapter 9 circuit design embedded array S1X60000 series epson 205 design guide ? vhdl description ? library ieee; library S1X60000_typ; use ieee.std_logic_1164.all use S1X60000_typ.primitives_tables.all; use S1X60000_typ.mos_switches.all; entity top is port ( clk ; in std_logic ; reset ; in std_logic ; ... ); end top; architecture rtl of top is component libcy port (pad : in std_logic; x: out std_logic); end component; component licrbf2 port (a : in std_logic; x: out std_logic); component clkgen port ( clk, aclk, bclk : in std_logic; ... ); end component; component aif port (.... ); end component; signal wclk, .....; begin pad1 : libcy port map ( pad ? clk, x ? iclk ); pad2 : u_clkgen : clkgen port map ( clk ? wclk, aclk ? aclk, ... ); u_aif : aif port map (aclk ? aclk, ... ); end rtl; chapter 9 circuit design 206 epson embedded array S1X60000 series design guide 9.11 pin layout and simultaneous operation this section describes the points to be noted in the layout of pins and the procedure for adding power supplies for simultaneous output-buffer operation. 9.11.1 estimating the number of power supply pins the necessary number of power supply pins must be estimated according to the lsi?s power consumption and the number of output buffers. in particular, a rather large transient current flows through the output buffers when they switch on or off. the amount of this transient current is greater for output buffers with greater drive capability. the number of power supply pins required for an lsi may be estimated with respect to its current consumption, as described below. (1) for single power supply systems letting the current consumption be i dd [ma], the number of power supply pins may be estimated with respect to this current consumption as follows: n idd i dd / 50 (pairs): with the v dd and v ss pins counted as one pair, 50 ma per pair can be supplied. notes 1: there must be at least four pairs of power supply pins, that is, one pair on each side of the lsi. i dd represents a value equal to the power consumption obtained in chapter 8, section 8.1, ?calculation of power consumption,? divided by the operating voltage. 2: if output buffers have dc loads connected to them with current steadily flowing, power supply pins must be added. for more information, contact the sales division of epson. (2) for dual power supply systems even for dual power supply systems, the allowable amount of current that can be flowed per pair of power supply pins (both hv dd and lv dd power supplies) is the same as that for single power supply systems. calculate the necessary number of power supply pin pairs separately for the hv dd and lv dd power supplies. (1) number of hv dd power supply pins letting the current consumption in the hv dd power supply system be i dd (hv dd ) [ma], the number of power supply pins, n idd (hv dd ), may be calculated with respect to this current consumption as follows: n idd (hv dd ) i dd (hv dd ) / 50: 50 ma per pin can be supplied (2) number of lv dd power supply pins letting the current consumption in the lv dd power supply system be i dd (lv dd ) [ma], the number of power supply pins, n idd (lv dd ), may be calculated with respect to this current consumption as follows: n idd (lv dd ) i dd (lv dd ) / 50: 50 ma per pin can be supplied (3) number of v ss power supply pins n idd (v ss ) {i dd (hv dd ) + i dd (lv dd )} / 50: 50 ma per pin can be supplied chapter 9 circuit design embedded array S1X60000 series epson 207 design guide notes 1: for the power supply pins hv dd , lv dd , and v ss , there must be at least four pairs of power supply pins, that is, one pair on each side of the lsi. i dd represents a value equal to the power consumption obtained in chapter 8, section 8.1, ?calculation of power consumption,? divided by the operating voltage. 2: if output buffers have dc loads connected to them with current steadily flowing, power supply pins must be added. for more information, contact the sales division of epson. 3: if it is necessary to add a power supply due to simultaneous changes in output, add the hv dd , lv dd , and v ss pins for each power supply system, separately for the hv dd output buffers and the lv dd output buffers. calculation example: the following shows an example of the procedure for estimating the number of power supply pins. here, the number of power supply pins is estimated using the power consumption obtained in chapter 8 for an ic, which has the following power supply characteristics. ? power-supply voltage: hv dd /lv dd = 3.3 v/2.5 v ? power consumption: p(hv dd ) = 224 [mw] p(lv dd ) = 684 [mw] (1) estimating the number of hv dd power supply pins letting the number of hv dd power supply pins be n idd (hv dd ), then n idd (hv dd ) = 224 [mw] / 3.3 [v] / 50 [ma] = 1.36 [pins] because there must be at least one power supply pin on each side of the ic, the number of hv dd power supply pins to be inserted is 4. (2) estimating the number of lv dd power supply pins letting the number of lv dd power supply pins be n idd (lv dd ), then n idd (lv dd ) = 684 [mw] / 2.5 [v] / 50 [ma] = 5.47 [pins] therefore, the number of lv dd power supply pins to be inserted is 6. (3) estimating the number of v ss power supply pins letting the number of v ss power supply pins be n idd (v ss ), then n idd (v ss ) = {224 [mw] / 3.3 [v] + 684 [mw] / 2.5 [v] } / 50 [ma] = 6.83 [pins] therefore, the number of v ss power supply pins to be inserted is 7 (however, we recommend that v ss pins be placed in pairs with the hv dd and lv dd power supply pins). thus, the respective numbers of power supply pins are as follows. hv dd power supply pins : 4 lv dd power supply pins : 6 v ss power supply pins : 7 chapter 9 circuit design 208 epson embedded array S1X60000 series design guide 9.11.2 simultaneous operation and adding power supplies the noise generated by output buffers when they switch on or off simultaneously may cause the lsi to operate erratically. this section describes the simultaneous operation of output buffers and the points to be noted when placing pins in order to suppress the noise induced by simultaneous output operation. 9.11.2.1 malfunction due to simultaneous operation when a number of output buffers change state simultaneously, a transient charging and discharging of current occurs due to load capacitance. the charging and discharging acts upon the inductance of the lead frame or bonding wire on the system?s substrate or package, resulting in the generation of noise. the noise thus generated is expressed by the equation below. vn = l dt di ... equation (1) where, vn: noise power supply l: power supply inductance component dt di : transient current here, because the transient current tends to increase in proportion to the number of simultaneously operating pins and their current drive capability and load capacitance, the voltage generated by the noise power supply varies depending on the following factors: (1) number of power supplies (2) number of simultaneously operating output buffers (3) drive capability of simultaneously operating output buffers (4) load capacitance of simultaneously operating output buffers inside the chi p transient current hv dd hv dd v ss output waveform hv dd v ss input waveform for the input buffer 4ns figure 9-13 noise due to simultaneous operation of outputs chapter 9 circuit design embedded array S1X60000 series epson 209 design guide 9.11.2.2 definition of simultaneous operation of outputs the simultaneous operation of outputs refers to a phenomenon in which multiple output buffers change state in the same direction within a certain time (i.e., within 4 ns). the simultaneous operation of outputs is defined independently for each closed loop of power supplies. the simultaneous operation of outputs in the same direction refers to the following operations: (1) h l, hz l, x l, or h x output signal operation (2) l h, hz h, x h, or l h output signal operation where, hz: high impedance x: indeterminate for bi-directional pins, the changeover of their functionality from input to output must also be taken into consideration. 9.11.2.3 restrictions on simultaneously operating output buffers the magnitude of the inductance of a closed loop in which output buffer charging and discharging current flows determines the magnitude of the generated noise. the inductance of a closed loop varies with the lsi?s pin layout and the board on which the lsi is mounted. to suppress the noise generated by the simultaneous operation of outputs, exercise caution in pin layout. a closed loop here refers to a pin layout in which output buffer pins are enclosed with the power supply pins at both ends. determine whether there is simultaneous operation of outputs independently for each closed loop of power supplies. vss g]` 1 vss g]` 2 ???????????????? vdd g]` 1 vdd g]` 2 ??? ? ???? closed loop between v ss 1 closed loop between v ss 2 x x x x x { z z x x z z { z z x x z z z z x x z z { x x x x x closed loop between v dd 1 closed loop between v dd 2 { : ground pins : power supply pins z : output buffers figure 9-14 closed loops consider a case in which output buffers are placed in the manner shown above and change state simultaneously, resulting in the generation of noise. to prevent malfunction of the lsi due to noise in this case, determine whether the magnitude of noise is sufficiently large to cause malfunction from the number of output buffers and the load capacitance in each closed loop, using the coefficients in tables 9-5 through 9-8 and the equation below. k mk 1 ... equation (2) where, mk: coefficient of each output buffer chapter 9 circuit design 210 epson embedded array S1X60000 series design guide for dual power supply systems, make this determination separately for the hv output cells in each closed loop between hv dd ?s, lv output cells in each closed loop between lv dd ?s, and for all output cells in each closed loop between v ss ?s. table 9-5 hv output cells, hv dd = 3.3 v 0.3 v load capacitance type 30 pf 50 pf 100 pf 150 pf 200 pf type s type m type 1 0.077 0.083 0.091 0.100 0.100 type 2 0.100 0.111 0.125 0.143 0.143 type 3 0.200 0.250 0.250 0.333 0.333 table 9-6 hv output cells, hv dd = 3.3 v 0.3 v (when using pci) load capacitance type 30 pf 50 pf 100 pf 150 pf 200 pf type s type m type 1 0.125 0.143 0.167 0.167 0.167 type 2 0.167 0.200 0.200 0.250 0.250 type 3 0.250 0.333 0.333 0.333 0.333 pci 0.167 0.200 0.200 0.250 0.250 note: this applies when a pci3v cell exists in the closed loop. table 9-7 lv output cells, v dd or lv dd = 2.5 v 0.2 v load capacitance type 30 pf 50 pf 100 pf 150 pf 200 pf type s type m type 1 0.077 0.083 0.091 0.100 0.100 type2 0.167 0.200 0.200 0.250 0.250 type3 0.250 0.333 0.333 0.333 0.333 table 9-8 lv output cells, v dd or lv dd = 2.0 v 0.2 v load capacitance type 30 pf 50 pf 100 pf 150 pf 200 pf type s type m type 1 0.050 0.054 0.059 0.065 0.065 type 2 0.084 0.100 0.100 0.125 0.125 type 3 0.162 0.216 0.216 0.216 0.216 chapter 9 circuit design embedded array S1X60000 series epson 211 design guide calculation example: determine whether the magnitude of noise is sufficiently large to cause malfunction due to the simultaneous operation of outputs under the following voltage and pin-layout conditions. ? power supply voltage : 3.3 v/2.5 v ? input interface : lvttl for hv cells cmos for lv cells pin no. cells used output load capacitance (pf) (1) v ss (2) hv dd (3) lv dd (4) hv cells, type 2 125 (5) hv cells, type 3 100 (6) hv cells, type 3 175 (7) hv dd (8) lv cells, type 1 75 (9) lv cells, type 3 150 (10) lv dd (11) v ss first, because tables 9-5 and 9-7 are used, round the output load capacitances up to the nearest whole value. (4) 125 pf 150 pf (5) 100pf 100 pf (6) 175 pf 200 pf (8) 75 pf 100 pf (9) 150 pf 150 pf ? make determination for the closed loop between hv dd ?s ((2) to (7)) the hv output cells used in the closed loop between hv dd ?s are (4), (5), and (6). from the input interface and the power supply voltage, make determination using the coefficients given in table 9-5. k mk = 0.143 + 0.250 + 0.333 = 0.726 thus, the result shows that the closed loop between hv dd ?s satisfies the determination criteria. chapter 9 circuit design 212 epson embedded array S1X60000 series design guide ? make determination for the closed loop between lv dd ?s ((3) to (10)) the lv output cells used in the closed loop between lv dd ?s are (8) and (9). from the input interface and the power supply voltage, make determination using the coefficients given in table 9-7. k mk = 0.091 + 0.333 = 0.424 thus, the result shows that the closed loop between lv dd ?s satisfies the determination criteria. ? make determination for the closed loop between v ss ?s ((1) to (11)) the output cells used in the closed loop between v ss ?s are (4), (5), (6), (8), and (9). from the input interface and the power supply voltage, make determination using the coefficients given in table 9-5 for the hv output cells, and table 9-7 for the lv output cells. k mk = 0.143 + 0.250 + 0.333 + 0.091 + 0.333 = 1.150 thus, the result shows that the noise restraints for malfunction due to the simultaneous operation of outputs are not met. therefore, change the pin layout by moving v ss at (11) to a position between (8) and (9) so that the cells in the closed loop between v ss ?s are (4), (5), (6), and (8). pin no. cells used output load capacitance (pf) (1) v ss (2) hv dd (3) lv dd (4) hv cells, type 2 125 (5) hv cells, type 3 100 (6) hv cells, type 3 175 (7) hv dd (8) lv cells, type 1 75 (11) v ss (9) lv cells, type 3 150 (10) lv dd make determination for the closed loop between v ss ?s in this pin layout. k mk = 0.143 + 0.250 + 0.333 + 0.091 = 0.817 thus, the result shows that the closed loop between v ss ?s satisfies the determination criteria. however, because v ss has been moved, the closed loop between v ss ?s comprised of cells (9) and below the cells (9) requires caution. vss moved to this point chapter 9 circuit design embedded array S1X60000 series epson 213 design guide 9.11.3 cautions and notes regarding the pin layout when the package to be used has been decided, the pin layout on it must also be decided. for details on the power supply pins and the number of usable input/output pins on each package in the S1X60000 series, refer to the designated ?pin layout table? fill-out sheet. when the pin layout has been decided, please provide epson with a ?pin layout table? after entering your pin layout on the designated sheet. because placement and routing work at epson is performed in accordance with the ?pin layout tables? received from customers, carefully inspect your pin layout table before presenting it to epson. when the designated ?pin layout table? fill-out sheet is required, please contact epson. the pin layout table is one of the important specifications determining the quality of the lsi. it is particularly important to prevent noise induced malfunction of the lsi. noise is a phenomenon that cannot easily be verified through simulation or the like. to prevent your lsi from operating erratically for unknown reasons, we recommend that the contents below be thoroughly examined prior to the creation of your pin layout. 9.11.3.1 fixed power supply pins depending on package combinations, there are several pins that can only be used for power supplies. furthermore, some of those pins are fixed for v dd use, while others are fixed for v ss use. therefore, check the ?pin layout table? fill-out sheet when selecting the package to use. 9.11.3.2 cautions and notes regarding the pin layout the pin layout may affect the logical functions or electrical characteristics of the lsi. furthermore, pin layout is subject to restrictions for reasons related to the lsi assembly or cell or bulk configurations. therefore, there are several parameters that require caution in the determination of pin layout. these parameters include power supply currents, the separation of input and output pins, critical signals, pull-up/pull-down resistance inputs, the simultaneous operation of outputs, and large-current drivers. the following describes these parameters. (1) power-supply currents (i dd , i ss ) the power supply currents (i dd , i ss ) specify the allowable value of the power supply current flowing in the power supply pins under operating conditions. if a current exceeding this allowable value flows in the power supply pins, the current density of the lsi?s internal power supply wiring increases, causing the reliability of the lsi to degrade or the lsi to break down. furthermore, the lsi?s internal voltage increases or decreases by an amount equal to the magnitude of voltage that develops due to the current and wiring resistance. it causes the functional blocks of the lsi to operate erratically or adversely affects the dc and ac characteristics of the lsi. to avoid these problems, the current density and the impedance of power supply wiring must be reduced. to this end, in the design of a circuit, estimate its power consumption and insert as many power supply pins as necessary to ensure that the current flowing in each power supply pin will not exceed the allowable value. for details on the power supply pins, refer to section 9.11.1, ?estimating the number of power supply pins.? in addition, make sure these power supply pins are well distributed, rather than being concentrated in one location. chapter 9 circuit design 214 epson embedded array S1X60000 series design guide it should be noted that the number of power supply pins ultimately required for the lsi is not simply the number of power supply pins determined above, but must also include the power supply pins that are added for noise protection purposes or the like. for details on the added power supply pins, refer to section 9.11.2, ?simultaneous operation and adding power supplies.? (2) noise generated by the operation of output cells the noise generated by the operation of output cells is broadly classified into the two types specified below. to reduce these types of noise, it is helpful to install as many power supply pins as possible. a) noise generated in the power supply lines the noise generated in the power supply lines presents a problem when there are multiple operating outputs. it causes the lsi?s input threshold level to change, which in turn causes the lsi to operate erratically. this type of noise is generated by a large current flowing into the power supply lines due to the simultaneous operation of output cells. power supply noise in particular is affected by the inductance component of the circuit. therefore, the lsi?s equivalent circuit can be expressed as shown in figure 9-15. when the output in this circuit diagram changes state from high to low, a current flows from the output pin into the lsi, with the current flowing through the equivalent inductance l2 (due to the lsi package or the like) to the ground. at this time, the equivalent inductance l2 causes the voltage of the lsi?s internal v ss power supply line to change. a voltage fluctuation occurring in this v ss power supply line is referred to here as the noise generated in the power supply line. because this type of noise is caused mainly by the equivalent inductance l2, there is a tendency that the greater the surge of the power supply current, the greater the magnitude of the noise generated. v dd input pin v dd internal output pin v ss internal v1 l1 l2 l3 figure 9-15 lsi equivalent circuit chapter 9 circuit design embedded array S1X60000 series epson 215 design guide b) overshoot, undershoot, and ringing noises known as overshoot, undershoot, or ringing are generated by the equivalent inductance at the output pins. l3 in figure 9-15 is an example of this equivalent inductance. because inductance has the property of storing energy, even when the output goes low or high, overshoots and undershoots are proportional to the magnitude of the current flowing in the output and the change in rate of the current due to the stored energy. the most efficient means of reducing overshoots and undershoots is the use of output cells with a small drive capability. overshoots and undershoots tend to decrease as the load capacitance increases. therefore, be particularly careful when using cells with a large drive capability. (3) isolating input and output pins separating the group of input pins from the group of output pins in design of the pin layout is an important technique for reducing the effect of noise. because the input pins and the bi-directional pins set for input are susceptible to noise, make sure they do not coexist with output pins in design of the pin layout. to this end, separate the group of input pins, the group of output pins, and the group of bi-directional pins according to the power supply pins (v dd , v ss ) when placing each group of pins. v ss v dd v dd v ss v dd v dd v ss v ss v dd v dd v ss v ss output pins input pins bid pins output pins figure 9-16 example of separating input and output pins (4) critical signals for critical signals such as input pins for clock and output pins operating at high speed, observe the precautions described below when placing pins. a) the clock and reset pins that are required to reduce the effects of noise must be placed away from the output pins at positions near the power supply pins. (figure 9-17) b) the input/output pins of the oscillation circuit (oscin, oscout) must be placed close to each other, enclosed with the power supply pins (v dd , v ss ). in addition, make sure that no output pins synchronous with the oscillation circuit are placed near these pins. (figure 9-18) chapter 9 circuit design 216 epson embedded array S1X60000 series design guide c) input and output pins operating at high speed must be placed near the center of one edge of the chip (package). (figure 9-17) d) if the delay from specific input pins to specific output pins has only a minimal margin with respect to the customer specification, these input and output pins must be placed close to each other. (figure 9-17) v ss clk through output high speed output v ss rs t through input high speed output figure 9-17 example 1 of a layout for critical signals v dd v ss oscin v ss oscout figure 9-18 example 2 of a layout for critical signals (5) pull-up/pull-down resistor inputs the pull-up/pull-down resistance values are rather large, ranging from several 10 k to several 100 k ? , and have dependency on the power supply voltage for reasons related to their structure. therefore, when using these inputs as test pins or for other purposes while they are left open, note the precautions described below, as these pins become susceptible to power supply noise and could cause the lsi to operate erratically. a) the pull-up/pull-down resistor inputs must be placed as far as possible from the high speed input signal pins (e.g., clock input pins). (figure 9-19) b) the pull-up/pull-down resistor inputs must be placed away from the output signal pins (particularly large-current output pins). (figure 9-20) in addition to the precautions on pin layout, take the following points into consideration as well. ? pull-up/pull-down resistor inputs must be processed on the circuit board (pcb) as much as possible. ? pull-up/pull-down resistors with small resistance values are preferable. chapter 9 circuit design embedded array S1X60000 series epson 217 design guide clk pull up figure 9-19 example 1 of placement of pull-up/pull-down resistors pull down high drive output figure 9-20 example 2 of placement of pull-up/pull-down resistors (6) simultaneous operation of outputs when multiple output pins operate simultaneously, they tend to generate noise, causing the lsi to operate erratically. when it is necessary to operate a number of output pins simultaneously, add power supply pins to the group of output pins that change state simultaneously, in order to prevent noise induced malfunction of the lsi. for details on the number of power supply pins to add and the procedure for placing the additional power supply pins, refer to section 9.11.2, ?simultaneous operation and adding power supplies.? as a means of reducing said noise, cells for delay use may be added in a stage preceding one group of output pins. this helps to reduce the number of output cells that change state simultaneously, thereby reducing the amount of noise generated. (figure 9-22) simultaneously changing output pins v ss v dd v ss v ss v dd v ss v ss v dd figure 9-21 example of adding power supply pins a out1 ta ts xtb3 at a out2 ta ts xtb 3 at dl1 figure 9-22 example of adding delay cells chapter 9 circuit design 218 epson embedded array S1X60000 series design guide (7) large current drivers when using the output of large current drivers (i ol = 12 ma, pci), observe the restrictions described below when placing pins. a) constraints on strengthening the power supplies large current drivers have large drive capability; therefore, the amount of noise generated by their output buffers during operation is also large. this noise may cause the lsi to operate erratically. when using large current drivers, add power supply pins near their pins in order to secure the power supply needed for the large current drivers. (figure 9-23) b) low noise pre-drivers to reduce the amount of noise generated by the output buffers of large current drivers during operation, low noise type output and bi-directional buffers available from epson may be used. for details, refer to chapter 4, ?types of input/output buffers and their use (x type)? and chapter 5, ?types of input/output buffers and their use (xf type).? v ss high drive outpu t v ss v dd v dd figure 9-23 example of strengthening power supplies (8) other precautions a) non-connection (nc) pins normally, leave the nc pins open on the circuit board. when making connections to nc pins as when mounting devices on a printed circuit board, make sure the pins are connected to v ss (gnd). note that when nc pins are connected to signal wiring or v dd (hv dd or lv dd ), leakage current may occur inside the chip. (see section 1.3.3, ?quiescent currents of input/output buffers (i qio ),? in chapter 1.) b) tab hanger pins tab hanger pins are pins on the package that are connected directly to the lsi substrate. these pins are tied to the v ss (gnd) level without being furnished with external power supplies for the aforementioned reasons. normally, leave these pins open on the board. chapter 9 circuit design embedded array S1X60000 series epson 219 design guide 9.11.4 example of the recommended pin layout pin layout is an important factor in ensuring that the lsi operates normally. the following shows a pin layout diagram (figure 9-24) based on the information given in this chapter. refer to this example in determining the pin layout. inp ut pins plup v dd inp 9 v ss v dd inp 10 inp 11 inp 12 inp 13 inp 14 clk inp 15 inp 16 inp 17 inp 18 inp 19 v dd bid0 v ss v dd bid1 bid2 bid3 bid4 ho ut out0 out1 mosc v dd v ss v ss v ss bid p ins out p ut p ins v ss inp 8 v ss v ss inp 7 inp 6 inp 5 oscin inp 4 inp 3 inp 2 inp 1 inp 0 v ss v dd oscout inp ut pins sout0 v ss sout1 v ss v ss sout2 sout3 sout4 sout5 sout6 sout7 sout8 sout9 v ss v dd v ss outp ut pins figure 9-24 example of the recommended pin layout input pins are placed on the top and left sides of the package, with the output pins changing simultaneously on its right sides, and the bi-directional pins and other output pins changing simultaneously on its bottom side. table 9-9 pin layout example placement pin name explanation of pin name detailed explanation of the placement of each pin plup input pins with pull-up placed at positions less affected by noise upper edge clk input pins for the clock placed near the center of the edge of the package or near the power supply pins oscin oscillator pin placed near the center of the edge of the package or near the power supply pins oscout oscillator pin placed near the center of the edge of the package or near the power supply pins left edge inp0?19 input pins placed apart from other pins, divided by power supply pins right edge sout0?9 simultaneously changing output pins placed apart from other pins, divided by power supply pins, with power supply pins added bid0?4 bi-directional pins placed apart from other pins, divided by power supply pins mosc oscillator monitor output pin placed near the power supply pins away from the oscillator pins hout high-drive output pin power supply pins placed nearby bottom edge out0-1 output pins placed apart from other pins, divided by power supply pins v dd v dd power supply pins overall edges v ss v ss (gnd) power supply pins chapter 9 circuit design 220 epson embedded array S1X60000 series design guide 9.12 about power supply cutoff (x type) when S1X60000 series cells (x type) are used to create a chip designed to power supply cut-off specifications, note the following. 9.12.1 for single power supply systems (1) in cases in which input signals from the outside also enter high-z state when the power supply is cut basically, all types of input/output buffers can be used. even in cases in which input/output buffers are separated by pairs of power supply pins and the power supply for part of the area is to be cut off, all types of input/output buffers can be used unless signals from the outside are applied. (however, this is possible providing that the power supplies for all of the related circuits, including the internal cell area, are cut-off.) (2) in cases in which input signals from the outside are applied when the power supply is cut off or pull-up resistors are incorporated external to the chip if input signals from the outside are applied while the power supply is cut off, leakage current may occur, depending on the type of input/output buffer used. therefore, the following types of input/output buffers cannot be used in this design: ? input buffers with pull-up resistors. however, this does not include fail-safe cells. ? output buffers other than fail-safe buffers. however, the open drain type can be used. ? bi-directional buffers other than fail-safe buffers. however, the open drain type can be used. (even in cases in which input/output buffers are separated by pairs of power supply pins and the power supply for part of the area is to be cut off, the input/output buffers listed above cannot be used in the relevant area.) 9.12.2 for dual power supply systems (1) in cases in which lv dd is cut off while hv dd remains on in this design, the output mode of the hv dd output buffers or hv dd bi-directional buffers may become uncontrollable. in the worst case scenario, current may even continue to flow into those buffers. therefore, the power supply cannot be cut off in this design. (2) in cases in which hv dd is cut off while lv dd remains on a) if inputs from the outside also enter high-z state when the hv dd power supply is cut off ? lv dd cells if the lv inputs also enter high-z state, use cells that include pull-up/pull-down resistors. no specific restrictions apply if lv inputs do not enter high-z state. ? hv dd cells be sure to use gated cells. current can be prevented from flowing at the initial input stage by setting control pin ?c? high or low in the internal circuit. chapter 9 circuit design embedded array S1X60000 series epson 221 design guide b) if input signals from the outside are applied when the hv dd power supply is cut off or pull-up resistors are incorporated external to the chip ? lv dd cells when lv inputs enter the high-z state, use cells that include pull-up/pull-down resistors. no specific restrictions apply if the lv inputs do not enter high-z state. ? hv dd cells for output buffers, use open drain type cells. for input buffers, also be sure to use gated cells. (note that input buffers with pull-up/pull-down resistors cannot be used.) current can be prevented from flowing at the initial input stage by setting control pin ?c? high or low in the internal circuit. bi-directional buffers cannot be used in this mode. for details on the gated mentioned above, refer to section 4.2.5, ?gated cells.? even in cases in which input/output buffers are separated by pairs of power supply pin and the power supply for part of the area is to be cut-off, no input/output buffers other than those mentioned above can be used in the relevant area. (3) in cases in which both hv dd and lv dd are cut-off a) if inputs from the outside also enter high-z state when the power supplies are cut-off basically, all types of input/output buffers can be used. even in cases in which input/output buffers are separated by pairs of power supply pins and the power supplies for part of the area are to be cut off, all types of input/output buffers can be used unless signals from the outside are applied. (however, this is possible provided that the power supplies for all of the related circuits, including the internal cell area, are cut off.) b) if input signals from the outside are applied when the power supplies are cut-off or pull-up resistors are incorporated external to the chip ? lv dd cells if input signals from the outside are applied while the power supplies are cut-off, leakage current may occur, depending on the type of input/output buffer used. therefore, the following types of input/output buffers cannot be used in this design: ? input buffers with pull-up resistors. however, this does not include fail-safe cells. ? output buffers other than fail-safe buffers. however, the open drain type can be used. ? bi-directional buffers other than fail-safe buffers. however, the open drain type can be used. ? hv dd cells as with lv dd cells, leakage current may occur depending on the type of input/output buffer used. the following types of input/output buffers cannot be used in this design. ? input buffers with pull-up resistors ? output buffers other than open drain buffers ? bi-directional buffers other than open drain buffers (even in cases in which input/output buffers are separated by pairs of power supply pins and the power supplies for part of the area are to be cut-off, the input/output buffers mentioned above cannot be used in the relevant area.) chapter 9 circuit design 222 epson embedded array S1X60000 series design guide 9.13 about power supply cutoff (xf type) when S1X60000 series cells (xf type) are used to create a chip designed to power supply cut-off specifications, note the following. 9.13.1 cell types usable during cut-off (1) in cases in which lv dd is cut-off while hv dd remains on in this design, the output mode of the hv dd output buffers or hv dd bi-directional buffers may become uncontrollable. in the worst case scenario, current may even continue to flow into those buffers. therefore, the power supply cannot be cut off in this design. (2) in cases in which hv dd is cut off while lv dd remains on a) if inputs from the outside also enter high-z state when the hv dd power supply is cut-off ? lv dd cells if the lv inputs also enter high-z state, use cells that include pull-up/pull-down resistors. no specific restrictions apply if lv inputs do not enter high-z state. ? hv dd cells be sure to use gated cells. current can be prevented from flowing at the initial input stage by setting control pin ?c? high or low in the internal circuit. ? 5 v tolerant fail safe cells all 5 v tolerant fail safe cells can be used. it is possible to shut off current flowing in the input circuit by setting control pin ?c? low in the internal circuit. (in this case, a high-level signal is forwarded to output pin ?x.?) note that control pin ?c? for 5 v tolerant fail safe cells must always be fixed high during normal operation. b) if input signals from the outside are applied when the hv dd power supply is cut-off or pull-up resistors are incorporated external to the chip ? lv dd cells if the lv inputs also enter high-z state, use cells that include pull-up/pull-down resistors. no specific restrictions apply if the lv inputs do not enter high-z state. ? hv dd cells (1) when handling hv dd input signals, be sure to use open drain type of cells for output buffers. also be sure to use gated cells for input buffers. bi-directional buffers cannot be used in this mode. (2) when handling 5.0 v input signals or using external 5.0 v pull up resistors, no hv dd cells can be used. chapter 9 circuit design embedded array S1X60000 series epson 223 design guide ? 5 v tolerant fail safe cells all 5 v tolerant fail safe cells can be used. it is possible to shut off current flowing in the input circuit by setting control pin ?c? low in the internal circuit. (in this case, a high level signal is forwarded to output pin ?x.?) hv dd input signals and 5.0 v input signals are both accepted. note that control pin ?c? for 5 v tolerant fail-safe cells must always be fixed high during normal operation. (3) in cases in which both hv dd and lv dd are cut-off a) if inputs from the outside also enter high-z state when the power supplies are cut-off basically, all types of input/output buffers can be used. even in cases in which input/output buffers are separated by pairs of power supply pins and the power supplies for part of the area are to be cut off, all types of input/output buffers can be used unless signals from the outside are applied. (however, this is possible provided that the power supplies for all of the related circuits, including the internal cell area, are cut-off.) b) if input signals from the outside are applied when the power supplies are cut-off or pull-up resistors are incorporated external to the chip ? lv dd cells if input signals from the outside are applied while the power supplies are cut-off, leakage current may occur, depending on the type of input/output buffer used. therefore, the following types of input/output buffers cannot be used in this design: ? input buffers with pull-up resistors. however, this does not include fail-safe cells. ? output buffers other than fail-safe buffers. however, the open drain type can be used. ? bi-directional buffers other than fail-safe buffers. however, the open drain type can be used. ? hv dd cells (1) for hv dd input signals, leakage current may occur depending on the type of input/output buffer used, as with lv dd cells. the following types of input/output buffers cannot be used in this design. ? 3v-pci cells and input buffers with pull-up resistors ? output buffers other than open drain buffers ? bi-directional buffers other than open drain buffers (even in cases in which input/output buffers are separated by pairs of power supply pins and the power supplies for part of the area are to be cut off, the input/output buffers mentioned above cannot be used in the relevant area.) (2) when handling 5.0 v input signals or using external 5.0 v pull up resistors, no hv dd cells can be used. chapter 9 circuit design 224 epson embedded array S1X60000 series design guide ? 5 v tolerant fail safe cells (1) when handling hv dd input signals, all 5 v tolerant fail safe cells can be used. note that control pin ?c? for 5 v tolerant fail-safe cells must always be fixed high during normal operation. (2) when handling 5.0 v input signals or using external 5.0 v pull up resistors, no hv dd cells can be used. chapter 10 circuit design that takes testability into account embedded array S1X60000 series epson 225 design guide chapter 10 circuit design that takes testability into account when ics are shipped from the epson factory, they are tested for product fitness through the use of an lsi tester. this requires that circuits be designed in consideration of the testability of the ic. therefore, be sure to take the points specified below into consideration in the design of a circuit. the contents described here do not apply to combined use with jtag circuits. if jtag circuits are desired, refer to section 10.8, ?boundary scan design,? and create test patterns that are capable of performing dc testing. furthermore, if test circuits cannot be added, contact the sales division of epson for confirmation. 10.1 consideration regarding circuit initialization although a number of flip-flops (ffs) are used in a circuit, the initial state of all ffs is x (indeterminate) when the circuit is tested using an lsi tester or simulated on a simulator. for this reason, depending on the circuit configuration, the circuit cannot be initialized or requires a huge number of test patterns for initialization. to avoid this problem, in the design of a circuit, be sure to use ffs with reset inputs or other means in order to enable the circuit to be initialized easily. 10.2 consideration regarding compressing the test patterns as the circuit size increases, so does the size of test patterns. be aware, however, that the size of test patterns is subject to the following limitations imposed by the use of an lsi tester. number of events per test pattern : up to 256k events number of test patterns : up to 30 total number of events in all test patterns : up to 1m events these limitations apply to test patterns for dc testing, including test patterns for z inspection, test patterns for test circuits, and test patterns for rom or megacells prepared by epson. for details on the number of rom or megacell test patterns and the number of events in those test patterns, contact the sales division of epson. for ram test patterns, note that although the reference patterns prepared by customers are subject to said limitations, the test patterns for complete ram pattern verification prepared by epson are not subject to limitations. in the design of a circuit, be sure to use an appropriate means of improving the circuit?s testability and thereby reducing the number of necessary test patterns by, for example, installing test pins that enable a clock to be input in the middle of a multi stage counter, or by adding test pins that allow the lsi?s internal signals to be monitored. 10.3 test circuit which simplifies dc and ac testing for the S1X60000 series, customers are expected to configure a test circuit and add it to the test circuit in order to allow shipment testing such as dc and ac testing by epson to be performed efficiently. if a test circuit cannot be added to your circuit, please contact epson for confirmation. chapter 10 circuit design that takes testability into account 226 epson embedded array S1X60000 series design guide 10.3.1 configuration of test circuits figure 10-1 shows the configuration of the test-mode control circuit ?tcir2? recommended by epson. figure 10-2 shows a typical test circuit with a test mode control circuit ?tcir2? and a 2 word 2 bit (this configuration is for illustrative purpose only) ram test circuit. refer to these circuits and (1) through (4) below when configuring a test circuit. if ram or functional cells are included in your circuit, also refer to section 10.4, ?memory block test circuits,? and section 10.6, ?function cell test circuits.? (1) adding and selecting pins for testing to configure pins for testing, add the four types of test pins specified below. for these test pins, select appropriate cells or buffers available. ? test enable input pin : 1 pin ? test mode select input pin : 4 pins ? monitor output pin for ac testing : 1 pin ? monitor output pin for dc testing : 1 pin table 10-1 test pins constraints test pin type number of pins name of pins (ex.) constraints, notes, etc. test enable input pin 1 pin tsten dedicated input pin. use itst1 for the input buffer. h: test mode; l: normal mode test mode select input pin 4 pins inp0 to inp3 input pin shareable with the user functions, but cannot be shared with bi-directional pins. avoid sharing this pin with other input pins that have a critical path. monitor output pin for ac testing 1 pin out3 input pin shareable with the user functions, but cannot be shared with n-channel open drain cells. type s and type m are not available. monitor output pin for dc testing 1 pin out4 input shareable with the user functions, but cannot be shared with bidirectional, 3-state terminal or n-channel open drain pins. output and input/output pins ? ? output buffer with test mode (bi-directional buffer used) ? dc testing this test checks whether all input and output pins satisfy the designated specifications for dc characteristics. if no test circuits are included, customers will be requested to create test patterns to enable measurement of dc characteristics, which may require a huge number of man-hours. use of a test circuit facilitates the creation of test patterns and therefore makes it easy to measure dc characteristics. ? ac testing this test involves measuring pin to pin delays (delays in input pins to output pins). if the actual operating frequency cannot be inspected using an lsi tester, the operating speed will be guaranteed by measuring the delay in a specific path. if the epson-recommended test circuit ?tcir2? is used, variations between lots will be chapter 10 circuit design that takes testability into account embedded array S1X60000 series epson 227 design guide evaluated by measuring the dedicated ac path using an ac test monitor output pin. because the recommended test circuit ?tcir2? does so by judging the difference in measured values between the tested device?s delay and the bypass delay, consistent delay measurement that is not dependent on the intra chip location of the test circuit or measurement conditions external to the chip is always possible. (2) adding and connecting a test-mode control circuit a: add a test mode control circuit (tcir2). b: connect output x pin and lg pin for the input buffer (itst1) of the dedicated test-mode input pin to the input tst pin and ilg pin of the ?tcir2?. c: connect the outputs for the input buffers of test-mode select input pins to the input pins of the test mode control circuit ?tcir2?. ? connect the x pin for the inp0 input buffer to the tm0 pin of the ?tcir2?. ? connect the x pin for the inp1 input buffer to the tm1 pin of the ?tcir2?. ? connect the x pin for the inp2 input buffer to the tm2 pin of the ?tcir2?. ? connect the x pin for the inp3 input buffer to the tm3 pin of the ?tcir2?. d: connect the output pins of the test-mode control circuit ?tcir2? to the input pins of the input/output buffers. ? connect the output pin (tac) of the tcir2 to the ta pin of the input/output buffer of the ac test monitor output pin (out3). ? connect the output pin (olg) of the tcir2 to the ta pins of the input/output buffer of the dc test monitor output pin (out4). ? connect the output pin (td) of the tcir2 to the ta pins of all input/output buffers other than the ac and dc test monitor output pins (out3 and out4). ? connect the output pin (te) of the tcir2 to the te pins of the input/output buffers for the 3-state pin (out2) and bi-directional pin (bid1). ? connect the output pin (ts) of the tcir2 to the ts pins of all input/output buffers. ? use the output pin (ms) of the tcir2 for control of each macro when ram or function cells are included in your circuit. e: even if the signals connected to the ta, te, or ts pins of input/output buffers exceed the fan-out limits, the violation of the fan-out limits can be ignored without causing any problem. (3) typical examples for setting test mode a: dc test ? quiescent current measurement mode *1 tsten ... high *1: when the macros to be installed include a quiescent current measurement mode, that measurement mode must be prepared separately. ? output characteristic (v oh /v ol ) measurement mode tsten ... high inp0 ... low inp1 ... high or low inp2 ... low measured pins *2 ... high or low chapter 10 circuit design that takes testability into account 228 epson embedded array S1X60000 series design guide *2: this includes all output and all bi-directional pins other than the dc test monitor output pin. ? input characteristic (v ih /v il ) measurement mode tsten ... high measured pins *3 ... low non-measured pin ... high dc test monitor output pin ... high or low *3: all input and all bi-directional pins (except tsten) must be tested. ? leakage current measurement mode tsten ... high inp0 ... high inp1 ... low inp2 ... high measured pins *4 ... high or low 3-state and nch open drain pins ... high impedance *4: this includes all 3-state output and all bi-directional pins other than inp0-2. b: dedicated ac test ? dedicated ac path measurement mode tsten ... high inp0 ... low inp1 ... low inp2 *5 ... change to high or low (input signal for the measured device) inp3 *5 ... select high (delay cell delay) or low (bypass delay) (measured device select pin) ac test monitor output pin ... outputs a signal corresponding to input for inp2. *5: after selecting the measured device using inp3, change inp2 to high or low in the next and subsequent events. in a pattern in which inp2 and inp3 change state simultaneously, delays cannot be measured accurately. refer to figure 10-3, ?example of the generation of a test pattern when there is a test option.? c: macro test ? macro-test mode tsten ... high inp0 ... high inp1 ... low inp2 ... low macro control pin in test mode *6 ... depends on the macro function macro watch pin in test mode *6 ... depends on the macro operation *6: this pin is assigned for macro control or watch in test mode. chapter 10 circuit design that takes testability into account embedded array S1X60000 series epson 229 design guide table 10-2 truth table for test circuit input output tst ilg tm3 tm2 tm1 tm0 ts td te tac olg ms 0 0 0 0 0 0 0 1 1 1 1 1 0 1 0 1 1 1 1 1 1 1 1 0 1 1 1 0 1 1 1 1 0 1 1 0 1 1 1 1 1 0 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 0 1 1 1 0 1 0 1 1 0 1 0 1 0 1 0 0 1 0 0 1 0 1 0 0 0 0 1 0 0 0 0 1 1 1 0 0 1 0 0 1 0 1 1 0 0 0 1 0 0 0 0 (4) generating the test patterns to ensure that dc and ac testing are conducted efficiently, customers will be requested to design both a test circuit and a test pattern. figure 10-3 shows a practical example of a test pattern for the example test circuit shown in figure 10-2. note the following points in generating the test pattern. a. generate a test pattern like the one shown in the example, separately from a pattern for circuit verification. b. this test pattern must contain a description of all pins used in the circuit. c. a test pattern for measuring both delay cell delay and bypass delay for ac testing is required. referring to figure 10-3, generate a test pattern that allows two pulses to be applied in each mode. d. in a pattern for circuit verification as well, write test pins (tsten). in such a case, the input level at the test mode select pin (tsten) must be set to logic 0 for selecting normal mode. e. when the input level for the test enable pin (tsten) is logic 1, all of the pull-up/pull-down resistors enter an inactive state. (5) circuit configuration of the test mode control circuit ?tcir2? shown in figure 10-1 is the circuit configuration of the test mode control circuit ?tcir2? recommended by epson. the tcir2 places the entire circuit in test mode and provides an efficient means of conducting dc and ac testing for the lsi. chapter 10 circuit design that takes testability into account 230 epson embedded array S1X60000 series design guide i_33 acp1b i_22 bf8 i_23 bf8 i_24 bf8 i_25 bf8 i_26 bf8 i_27 bf8 i_15 or2 i_16 an222 i_21 no2 i_17 no2 i_1 no2 i_2 in2 i_18 no3 i_6 no2 i_19 no2 i_20 no2 i_28 na2 i_29 na2 i_30 na2 i_7 na2 i_31 in1 i_32 in1 i_9 in1 i_8 in1 i_10 bf1 i_11 bf1 i_12 bf1 tm0 tm1 tm2 ms td te ts tac tm3 tst olg ilg figure 10-1 internal circuit of the tcir2 chapter 10 circuit design that takes testability into account embedded array S1X60000 series epson 231 design guide i_32 itst1 i_33 tcir2 ilg tm0 tm1 tm2 tm3 tst ms olg tac td te ts i_30 ob1t a ta ts i_31 ob1t a ta ts i_1 ob1t a ta ts i_2 ob1t a ta ts i_3 tb1t a e ta te ts i_4 bc1t a e ta te ts i_5 ao24a i_6 ao24a i_12 ao24a i_13 ao24a i_7 ao24a i_8 ao24a i_9 ao24a i_10 ao24a i_11 ao24a i_14 ao24a i_15 ao24a i_16 ao24a i_17 ao24a i_18 ao24a i_19 ram1p1 a0 a1 a2 a3 a4 a5 cs d0 d1 d10 d11 d12 d13 d14 d15 d2 d3 d4 d5 d6 d7 d8 d9 rw y0 y1 y10 y11 y12 y13 y14 y15 y2 y3 y4 y5 y6 y7 y8 y9 i_20 ram1p1 a0 a1 a2 a3 a4 a5 cs d0 d1 d10 d11 d12 d13 d14 d15 d2 d3 d4 d5 d6 d7 d8 d9 rw y0 y1 y10 y11 y12 y13 y14 y15 y2 y3 y4 y5 y6 y7 y8 y9 i_34 ibc i_35 ibc i_36 ibc i_21 ibc i_24 ibc i_25 ibc i_26 ibc i_27 ibc i_28 ibc i_22 ibc i_23 ibc ia0 bid1 id0 id1 out0 irw1 ics1 out1 out2 irw2 out3 ics2 out4 inp0 inp1 inp2 inp3 tsten lg x customer s circuit figure 10-2 example of a test circuit chapter 10 circuit design that takes testability into account 232 epson embedded array S1X60000 series design guide z z z z example of the apf format # example of test pattern for ac & dc test by tcir2 $rate 200000 $resolution 0.001ns $strobe 185000 $node tsten id 0 inp0 i 0 inp1 i 0 inp2 i 20000 #difference measurement inp3 i 0 ia 0 i 0 id 0 i 0 id 1 i 0 ics1 i 0 ics2 i 0 irw1 i 0 irw2 i 0 bid1 b 0 out0 o out1 o out2 o out3 o out4 o $endnode $pattern # tiiiiiiiiiiibooooo # snnnnaddccrriuuuuu # tpppp001sswwdttttt # e0123 1212101234 # n # # iiiiiiiiiiiibooooo # u # 0 00000.......xxxxxx 1 10000.......lllllx : dedicated ac path measurement 1 (bypass) 2 10010.......llllhx 3 10000.......lllllx 4 10001.......lllllx : dedicated ac path measurement 2 (delay path) 5 10011.......llllhx 6 10001.......lllllx 7 11010.......0zhhhx : off state leakage-current measurement 8 11010.......1zhhhx 9 10000.......lllllx : output characteristic measurement 10 10100.......hhhhhx $endpattern # # eof note: the ?.? denotes logic 1 or 0. figure 10-3 example of the generation of a test pattern when there is a test option chapter 10 circuit design that takes testability into account embedded array S1X60000 series epson 233 design guide 10.4 memory block test circuits 10.4.1 basic cell type ram when a ram is used it is necessary to test all bits before shipping the product. ram terminals must be accessible via primary i/o pins. ram test circuitry can be implemented, which multiplexes existing pin functionality with direct ram access functionality so as to avoid increasing the designs pin count. no bi-directional pins can be used for input as they all are placed in an output state during ram test. if input pins are inadequate, attach a control circuit to the target bi-directional te pin. also, when multiple rams are used, we recommend that each ram?s pins be accessible via unique i/o pins. however, when the number of external i/o pins is inadequate, each ram?s pins may share common external i/o pins. the example test circuit in figure 10-2 performs normal operations unless in test mode; when placed in test mode, the circuit allows data to be written directly to ram from external pins ics1-2, irw1-2, id0-1, and ia0. at the same time, ram output in this circuit can be read out to external pins ay0 and ay1. although it is possible to share the ram pins with bi-directional pins or 3-state output pins, it is necessary to tie the bi-directional pins to either an input or an output state during ram test. however, please do not allocate an input buffer with a pull-up resistor to cs, because doing so would make it impossible to measure the quiescent current. 10.4.1.1 ram test patterns after incorporating ram test circuitry, it is necessary to make test patterns for both the normal operating state and the test state of the chip. checks are performed in the normal state to verify the connection with the customer?s circuits, and are performed to insure that the test circuit is correct in the test state. also, we request a test pattern to serve as a template when epson generates the ram test pattern. note that there are asynchronous 1 port and 2 port types, and synchronous 1 port and 2 port types of basic cell type ram, and for each of which the method of creating a test pattern differs. figures 10-4 and 10-5 show the procedures for creating test patterns for asynchronous type ram; figures 10-6 and 10-7 show those for synchronous type ram. chapter 10 circuit design that takes testability into account 234 epson embedded array S1X60000 series design guide x (1) setup a [2 : 0] rw cs d [3 : 0] y [3 : 0] x (read data) strobe expect (2) write (3) read the tester may perform repetitive write operations with the timing shown in the timing chart on the right. the timing of the rw signal should take this into account. x (2) write (2) write timing chart this pattern serves as a template for 1 port ram tests. $rate 200000 $strobe 185000 $resolution 0.001ns $node inpa i 0 inpb i 0 inpc i 0 inpd i 0 inpe i 0 inpf i 0 inpg i 0 inph n 20000 120000 inpi i 0 . . outa 0 outb 0 outc 0 outd 0 . . $endnode $pattern # # # aaaddddrc yyyy 0120123ws 0123 0 000101010..xxxx.. 1 0001010n1..xxxx.. 2 000101011..hlhl.. 3 101111110..xxxx.. 4 1011111n1..xxxx.. 5 101111111..hhhh.. 6 111010110..xxxx.. 7 1110101n1..xxxx.. 8 111010111..lhlh.. example of apf format please provide all i/o pins used in performing simulation. reference the timing chart below to set timing. it is useful to place comments here. when a sequence is necessary to set the test mode, input the pattern here. [1] access the lowest address, a middle address and the highest address. [2] structure a single access from 3 events (test cycles). in the first event, set the data and the address. in the next event, perform a write. in the third event, perform a read. [3] use an rz waveform to describe the rw signal so that the write operation can be completed in a signal event. [4] change the data to be written for each address tested. [5] verify that the results are the same as expected form the results of the simulations. figure 10-4 generating 1 port ram test pattern chapter 10 circuit design that takes testability into account embedded array S1X60000 series epson 235 design guide x (1) setup cs x (read data) (2) write (2) write (2) write (3) read the tester may perform repetitive write operations with the timing shown in the timing chart on the right. the timing of the wr signal should take this into account. x all 1 ra [2 : 0] wr y [3 : 0] d [3 : 0] strobe expect rd wr [2 : 0] this pattern serves as a template for 2 port ram tests. timing chart $rate 200000 $strobe 185000 $resolution 0.001ns $node inpa i 0 inpb i 0 inpc i 0 inpd i 0 inpe i 0 inpf i 0 inpg i 0 inph i 0 inpi i 0 inpj i 0 inpk i 0 inpl p 20000 120000 inpm i 0 . . outa 0 outb 0 outc 0 outd 0 . . $endnode $pattern # # # # rrrwww aaaaaaddddrwc.yyyy.. 0120120123drs.0123.. 0 0000001010000.xxxx.. 1 00000010100p1.xxxx.. 2 0000001111101.hlhl.. 3 1011011111000.xxxx.. 4 10110111110p1.xxxx.. 5 1011010000101.hhhh.. 6 1111110101000.xxxx.. 7 11111101010p1.xxxx.. 8 1111111111101.lhlh.. it is useful to place comments here. when a sequence is necessary to set the test mode, input the pattern here. [1] access the lowest address, a middle address and the highest address. [2] structure a single access from 3 events (test cycles). in the first event, set the data and the address. in the next event, perform a write. in the third event, perform a read. [3] use an rz waveform to describe the rw signal so that the write operation can be completed in a signal event. [4] change the data to be written for each address tested. [5] verify that the results are the same as expected form the results of the simulations. [6] set all bits of data to "1" when reading. however, if all bits of the data to write are 1?s, all bits of data during reading must be 0?s. example of apf format please provide all i/o pins used in performing simulation. reference the timing chart below to set timing. figure 10-5 generating 2 port ram test pattern chapter 10 circuit design that takes testability into account 236 epson embedded array S1X60000 series design guide z z z z this pattern serves as a test template. y timing chart a [n:0] d[m:0] ck xcs xwe y[m:0] strobe r ecommen d e d va l ues f or t 0 t o t 3 : t 0 = 200 ns, t 1 = 20 ns, t 2 = 100 ns, t 3 = 185 ns y example for apf format (16 words x 4 bits) $ rate 200000 $ strobe 185000 $ resolution 0.001ns $ node ia3 i 0 ia2 i 0 ia1 i 0 ia0 i 0 ick p 20000 120000 ixcs i 0 ixwe i 0 id3 i 0 id2 i 0 id1 i 0 id0 i 0 ??? oy3 o oy2 o oy1 o oy0 o $ endnode $ pattern # aaaacxxdddd ??? yyyy # 3210kcw3210 ??? 3210 # se 0 00000010000 ??? xxxx 1 0000p100000 ??? xxxx 2 0000p110000 ??? llll 3 01010010101 ??? xxxx 4 0101p100101 ??? xxxx 5 0101p110101 ??? lhlh 6 11110011111 ??? xxxx 7 1111p101111 ??? xxxx 8 1111p111111 ??? hhhh $ endpattern (1) dummy event (2) write event (3) read event t 0 t 3 t 1 t 2 old data(don't care) write through data valid dat a a ccess the test pattern for the dummy, write, and read events in one operation (one tester cycle) and perform the test three times: first the lower address, then the middle address, then the upper address. set the address and data at the beginning of a dummy event, write the data in a write event, and read the data in a read event. a pply ck as a pulse (rz waveform). change the write data after each access operation. if there is a test mode setup sequence, be sure to insert it prior to event 0. (event numbers need to be reassigned.) a fter creating a test pattern, always confirm its functionality through logic simulation. when simulated, the test pattern will produce an output during a dummy event (old data) and an output during a write event (write- through data). however, because these outputs do not need to be verified, we recommend that they be rewritten to indeterminate values before being interfaced to the tester. be sure to write all i/o pins to ensure that simulations are performed. (1) (2) (3) (4) (6) (5) figure 10-6 procedure for creating test patterns for 1 port ram (synchronous) test pattern chapter 10 circuit design that takes testability into account embedded array S1X60000 series epson 237 design guide z z z z thi s pa tt ern serves as a t es t t emp l a t e. y y y y ti m i ng c h art aa,ab[n:0] d[ m: 0] c ka ckb xwa xrb y[ m: 0] s trobe recommended values for t 0 ? t 3 : t 0 = 200 ns, t 1 = 20 ns, t 2 = 100 ns, t 3 = 185 ns y y y y e xamp l e f or apf f orma t (16 wor d s x 4 bit s ) $rate 200000 $strobe 185000 $resolution 0.001ns $node ia3 i 0 ia2 i 0 ia1 i 0 ia0 i 0 icka p 20000 120000 ixwa i 0 id3 i 0 id2 i 0 id1 i 0 id0 i 0 ??? iab3 i 0 iab2 i 0 iab1 i 0 iab0 i 0 ickb p 20000 120000 ixrb i 0 oy3 o oy2 o oy1 o oy0 o $endnode $pattern # aaaacxdddd ??? aaaacxyyyy # aaaakw3210 ??? bbbbkr3210 # 3210ae ??? 3210bb 0 0000010000 ??? 000001xxxx 1 0000p00000 ??? 000001xxxx 2 0000010000 ??? 0000p0llll 3 0101010101 ??? 010101xxxx 4 0101p00101 ??? 010101xxxx 5 0101010101 ??? 0101p0lhlh 6 1111011111 ??? 111101xxxx 7 1111p01111 ??? 111101xxxx 8 1111011111 ??? 1111p0hhhh $endpattern t 3 old data(don't care) write through data valid dat a t 1 t 2 t 1 t 2 (1) dummy event (2) write event (3) read event t 0 access the test pattern for the dummy, write, and read events in one operation (one tester cycle) and perform the test three times: first the lower address, then the middle address, then the upper address. set the address and data at the beginning of a dummy event, write the data in a write event, and read the data in a read event. apply ck as a pulse (rz waveform). change the write data after each access operation. if there is a test mode setup sequence, be sure to insert it prior to event 0. (event numbers need to be reassigned.) after creating a test pattern, always confirm its functionality through logic simulation. when simulated, the test pattern will produce an output during a dummy event (old data) and an output during a write event (write- through data). however, because these outputs do not need to be verified, we recommend that they be rewritten to indeterminate values before being interfaced to the tester. be sure to write all i/o pins to ensure that simulations are performed. (1) (2) (3) (4) (6) (5) figure 10-7 procedure for creating 2 port ram (synchronous) test pattern chapter 10 circuit design that takes testability into account 238 epson embedded array S1X60000 series design guide 10.4.2 standard type 1 port ram for standard type 1 port ram, as for basic cell type ram, please incorporate a test circuit which can be accessed directly from external pins and create test patterns in both normal and test states. (epson will use the test state test patterns as templates as it creates dedicated ram test patterns.) (for details, refer to section 10.4.1, ?basic cell type ram.?) when creating test-state test patterns for standard-type 1 port ram, please follow the prescribed procedure. z z z z this pattern serves as a test template. y timing char t a[n:0] d[m:0] ck xc s xwe y[m :0 ] strobe recommended values for t 0 to t 3 : t 0 = 200 ns, t 1 = 20 ns , t 2 = 100 ns, t 3 = 185 ns y example for apf format (16 words x 4 bits) $ rate 200000 $ strobe 185000 $ resolution 0.001ns $ node ia3 i 0 ia2 i 0 ia1 i 0 ia0 i 0 ick p 20000 120000 ixcs i 0 ixwe i 0 id3 i 0 id2 i 0 id1 i 0 id0 i 0 ??? oy3 o oy2 o oy1 o oy0 o $ endnode $ pattern # aaaacxxdddd ??? yyyy # 3210kcw3210 ??? 3210 # se 0 00000010000 ??? xxxx 1 0000p100000 ??? xxxx 2 0000p110000 ??? llll 3 01010010101 ??? xxxx 4 0101p100101 ??? xxxx 5 0101p110101 ??? lhlh 6 11110011111 ??? xxxx 7 1111p101111 ??? xxxx 8 1111p111111 ??? hhhh $ endpattern (1) dummy event (2) write event (3) read event t 0 t 3 t 1 t 2 old data(don't care) write through data valid data access the test pattern f or the dummy, w rite, and read events in one operation (one tester cycle) and perf orm the test three times: f irst the low er address, then the middle address, then the upper address. set the address and data at the beginning of a dummy event, w rite the data in a w rite event, and read the data in a read event. apply ck as a pulse (rz w aveform). change the w rite data after each access operation. if there is a test mode setup sequence, be sure to insert it prior to event 0. (event numbers need to be reassigned.) after creating a test pattern, alw ays confirm its functionality through logic simulation. when simulated, the test pattern w ill produce an output during a dummy event (old data) and an output during a w rite event (w rite-through data). how ever, because these outputs do not need to be verified, w e recommend that they be rew ritten to indeterminate values before being interfaced to the tester. be sure to w rite all i/o pins to ensure that simulations are performed. (1) (2) (3) (4) (6) (5) figure 10-8 procedure for creating test patterns for standard type 1 port ram chapter 10 circuit design that takes testability into account embedded array S1X60000 series epson 239 design guide 10.4.3 standard type dual port ram for standard type dual port ram, as for basic cell type ram, please incorporate a test circuit which can be accessed directly from external pins and create test patterns in both normal and test states. (epson will use the test state test patterns as templates as it creates dedicated ram test patterns.) (for details, refer to section 10.4.1, ?basic cell type ram.?) when creating test state test patterns for standard type dual port ram, although essentially the same procedure applies as is described in section 10.4.2, ?standard type 1 port ram,? please follow the specific procedure described below, so that test patterns will be created separately (depending on how the ports are used). (1) when using as dual port ram (reading and writing on both ports a and b), create the following two test patterns:* ? test pattern 1: write from port a, read from port a ? test pattern 2: write from port b, read from port b (2) when using as 2 port ram (writing on port a, reading on port b), create the following (one) test pattern. ? test pattern 1: write from port a, read from port b (3) when using as 3 port ram (reading and writing on port a, reading on port b), create the following two test patterns:* ? test pattern 1: write from port a, read from port a ? test pattern 2: write from port a, read from port b * to prevent possible simultaneous access of the same address, please avoid writing the same test pattern for test patterns 1 and 2. 10.4.4 high density type ram for high density type ram, as for basic cell type ram, please incorporate a test circuit which can be accessed directly from external pins and create test patterns in both normal and test states. (the test state test patterns become a template which epson will use as it creates dedicated ram test patterns.) (for details, refer to section 10.4.1, ?basic cell type ram.?) regarding test state test patterns for the high density type ram, essentially the same procedure applies as is described in section 10.4.2, ?standard type 1 port ram.? 10.4.5 mask rom for mask rom, as for basic cell type ram, please incorporate a test circuit which can be accessed directly from external pins and create test patterns in both normal and test states. (for details, refer to section 10.4.1, ?basic cell type ram.?) chapter 10 circuit design that takes testability into account 240 epson embedded array S1X60000 series design guide when creating the mask rom test state test patterns, please follow the procedure described below in order to ensure that data can be read out from all addresses. y y y y timing chart a [n:0] c k x cs y[m:0] s trobe recommended values for t 0 ?t 3 : t 0 = 200 ns, t 1 = 20 ns, t 2 = 100 ns, t 3 = 185 ns y example f or apf f ormat ( 16 words x 4 bits ) $ rate 200000 $ strobe 185000 $ resolution 0 . 001 ns $ node ia 3 i 0 ia 2 i 0 ia 1 i 0 ia 0 i 0 ick p 20000 120000 ixcs i 0 ??? oy 3 o oy 2 o oy 1 o oy 0 o $ endnode $ pattern # aaaacx ??? yyyy # 3210 kc ??? 3210 # s 0 0000 p 0 ??? llhh 1 0001 p 0 ??? llhl 2 0010 p 0 ??? llll 3 0011 p 0 ??? lhll ??? 12 1100 p 0 ??? hhhl 13 1101 p 0 ??? hhlh 14 1110 p 0 ??? hlhh 15 1111 p 0 ??? lhhh $ endpattern t 3 read event valid data t 0 t 1 t 2 perform read operations on all addresses, based on the read event shown above. addresses may be changed in any order, as desired. ck must be applied as a pulse (rz waveform). there is no need to stop the clock. if there is a test-mode setup sequence, be sure to insert it prior to event 0. (event numbers need to be reassigned.) be sure to write all i/o pins to ensure that simulations are performed. (1) (2) (3) figure 10-9 procedure for creating mask rom tes patterns chapter 10 circuit design that takes testability into account embedded array S1X60000 series epson 241 design guide 10.5 memory bist design the S1X60000 series comes equipped with a memory self diagnostic circuit called the ?memory bist (built in self test),? which may be used as a test circuit for testing the lsi?s internal memory. use of the memory bist provides numerous advantages, including those specified below. ? eliminates the need for customers to design a memory test circuit ? allows the number of external pins for memory testing to be reduced ? capable of testing memory at an actual high operating speed ? allows the time required for memory testing using an lst tester to be reduced in addition, it offers versatile optional functions such as a bypass circuit (transparent circuit) for memory inputs, as a means of increasing fault detection rates for the entire chip. *1 note *1: if fault detection rates are to be increased, the lsi must be modified so as to be suitable for scan testing following the insertion of a bypass circuit. if it is necessary to make the entire chip suitable for scan testing, a bypass circuit must also be optionally included in the memory bist. 10.5.1 outline of the memory bist circuit block the memory bist generates a circuit known as a ?collar? in the periphery of the memory, and a circuit known as a ?controller? that controls the collar. if multiple pieces of memory are included, multiple collars are generated that can be controlled by a single controller (for purposes of overhead reduction). in addition, a bypass circuit or a fault diagnosis function may be added to inputs for memory as necessary. under no circumstances can the number of elements inserted for memory inputs exceed the number of multiplexer stages, however. when the memory bist is inserted, a circuit block becomes similar to that depicted in figure 10-10, and a bypass circuit becomes similar to that depicted in figure 10-11 (in both, memory bist design is applied to synchronous type ram). chapter 10 circuit design that takes testability into account 242 epson embedded array S1X60000 series design guide figure 10-10 block diagram after insertion of the memory bist circuit sram bist_clk mux xcs xwe dn am yn ck lv_tm figure 10-11 bypass circuit chapter 10 circuit design that takes testability into account embedded array S1X60000 series epson 243 design guide 10.5.2 outline of the memory bist circuit test sequence memory testing is started by applying a clock to the memory bist and memory devices, and driving the enable signal (mbist_en) from low to high. immediately after testing begins, the test judge signal (mbist_go) goes high and the test end signal (mbist_done) goes low. provided that the test is performed normally, the judge and end signals do not change state until completion of the test. conversely, if any problem is encountered in the test, the judge signal goes low (once the judge signal has gone low, it never returns high). testing is completed when the end signal goes high. if the judge signal is held high at this time, the test has terminated normally; if it is held low, a problem has been encountered in the test. the test sequence of the memory bist is similar to that depicted in figure 10-12. when in error, mbist_go is dropped low (not released back high) when test ends normally, mbist_go remains high. bist_clk mbist_en mbist_done mbist_go mbist_go driving mbist_en high starts the test. test completed when mbist_done goes high test period (when terminated normally) (when terminated in error) figure 10-12 test sequence of the memory bist circuit 10.5.3 types of memory suitable for memory bist the types of memory available from epson that are suitable for the memory bist are listed below. (*2) ? synchronous 1 port/2 port sram of the basic cell type ? synchronous 1 port/dual-port sram of the standard type ? high density type of synchronous 1 port sram ? synchronous mask rom (*3) notes *2: certain types of memory other than those listed above are suitable for bist. for more information, contact the sales division of epson. *3: for mask rom, if rom data is modified, the bist circuit must be regenerated, as it contains the expected signatured values. 10.5.4 estimating the memory bist circuit size the circuit size of the memory bist circuit varies significantly depending on the type and number of srams, the test configuration, the bist circuit options, and the limitations on logic synthesis. for more information, contact the sales division of epson. for estimates, refer to table 10-3, which lists the typical memory bist circuits and circuit sizes in the respective cases. chapter 10 circuit design that takes testability into account 244 epson embedded array S1X60000 series design guide table 10-3 circuit sizes of typical memory bist circuits typical memory configuration number of pcs. number of collar gates number of controller gates total synchronous 1 port 1024 words x 8 bits 5 1210 1553 2763 synchronous 1 port 1024 words x 8 bits 10 2420 1723 4143 synchronous 1 port 1024 words x 8 bits 20 4840 1888 6728 synchronous 1 port 1024 words x 8 bits 40 9680 2219 11899 synchronous 1 port 1024 words x 32 bits 5 2970 3471 6441 synchronous 1 port 1024 words x 32 bits 10 5940 4081 10021 synchronous 1 port 1024 words x 32 bits 20 11880 4624 16504 synchronous 1 port 1024 words x 32 bits 40 23760 5766 29526 synchronous dual-port 1024 words x 8 bits 5 2500 1571 4071 synchronous dual-port 1024 words x 8 bits 10 5000 1745 6745 synchronous dual-port 1024 words x 8 bits 20 10000 1910 11910 synchronous dual-port 1024 words x 8 bits 40 2000 2254 22254 synchronous dual-port 1024 words x 32 bits 5 6335 3491 9826 synchronous dual-port 1024 words x 32 bits 10 12670 4102 16772 synchronous dual-port 1024 words x 32 bits 20 25340 4646 29986 synchronous dual-port 1024 words x 32 bits 40 50680 5802 56482 ? the number of gates shown above is the result of logic synthesis performed using the basic cell type msi cell. ? in each case, the circuit is configured with a single controller. ? in each case, a bypass circuit (for scan testing) is added. ? if 1 port and dual-port memory coexist, estimate the necessary number of gates by adding up both gate numbers for collar gates, or using dual port gate number alone for controller gates. 10.5.5 about memory bist circuit design at epson, memory bist is inserted for the rtl or gate level netlists received from customers. to facilitate this operation, customers will be requested to exercise caution in the design of a circuit, as described below. 1) test input/output pins for the memory bist in memory bist, bist_clk is normally substituted for by the memory clock (system clock). therefore, the test input/output pins required for the memory bist are basically the following three (*3) : ? mbist_en (mode set signal): input pin ... dedicated pin recommended (or can be shared with another pin if the necessary conditions are met) ? mbist_go (test judge signal): output pin ... can be shared with another pin ? mbist_done (test end signal): output pin ... can be shared with another pin chapter 10 circuit design that takes testability into account embedded array S1X60000 series epson 245 design guide furthermore, if a bypass circuit is optionally included, the pin specified below is required. however, this pin is unnecessary if it is separately assigned when the entire chip is made suitable for scan testing. ? lv_tm (scan mode set signal): input pin ... can be shared with the scan mode set pin for the entire chip to facilitate design, we recommend that mbist_en be provided as a dedicated pin. if it is necessary that mbist_en be shared with another pin, the entire circuit, including the customer?s circuit, must be configured so as to satisfy the following initialization requirements: ? memory bist can be set to mbist_en = 0 (normal operation mode) and bist_clk (= memory clock) can be applied to at least two pulses. ? after the above operation has been conducted, the memory bist can be set to mbist_en = 1 (bist mode) and bist_clk (= memory clock) can be applied continuously. 2) restrictions during normal operation circuits are added in the periphery of memory when memory bist is applied, and this peripheral circuit must be initialized in normal operation, not just in bist mode (unless it is initialized, the memory cannot be accessed during simulation). therefore, the entire circuit, including the customer?s circuit, must be configured so as to satisfy the following initialization requirements (*4) : ? memory bist can be set to mbist_en = 0 (normal-operation mode) and bist_clk (= memory clock) can be applied to at least two pulses. 3) skew adjustment of the memory clock because the memory bist circuit (collars and controller) is comprised of multiple sequential circuits, clock skews must be adjusted between the memory?s clock signal and the clock signals for the internal flip-flops of the bist circuit (collars and controller). therefore, make sure the clock for the memory to which memory bist is to be applied is designed for optimization by clock tree synthesis. for more detailed contents of the design, refer to the application cases described below. (1) if multiple system clocks are associated with memory operation in the circuit, clock skews are generally adjusted by assigning one bist controller to each clock (multiple bist controllers as a whole). in such a case, the circuit must be configured so as to allow clock skews to be adjusted individually for each memory clock. (2) even when multiple system clocks are associated with memory operation in the circuit, if the clocks can be integrated into one line for operation in bist mode, the memory bist circuit can be configured with a single bist controller. in such a case, the circuit must be configured so as to allow clock skews to be adjusted for all memory clocks in bist mode. chapter 10 circuit design that takes testability into account 246 epson embedded array S1X60000 series design guide (3) in cases in which multi-port memory has different clocks for the respective ports, the clock skews must be adjusted using a multiplexer. in such a case, insert a multiplexer for clocks other than the selected clock. notes *3: although the bist circuit requires bist_clk as its clock input when operating singly, bist_clk can normally be substituted for by the memory clock (system clock) or other internal clock, as initialization, skew adjustment, and the like are required. furthermore, if the bist circuit is configured with multiple bist controllers, there must be as many mbist_go and mbist_done outputs as the number of bist controllers. for mbist_en input, however, a single input will suffice. *4: this circuit configuration can also include initialization of the customer?s own circuit. if the required circuit configuration cannot be designed, contact the sales division of epson. 10.5.6 other ? memory bist can be applied without concern for the restrictions associated with hierarchical design, regardless of where in the customer?s circuit memory exists. ? it does not matter whether the customer?s circuit contains memory for which memory bist is applied or memory for which memory bist is not applied. ? before memory bist can be inserted, customers will be requested to furnish epson with temporary rtl or temporary netlists for the purpose of preliminary examination. a period of approximately three days is required for preliminary examination. following completion of preliminary examination, a period of approximately one day is required for insertion of the bist circuit. furthermore, to facilitate insertion of memory bist, customers are requested to present the checksheet attached herein, along with said temporary rtl or temporary netlists. chapter 10 circuit design that takes testability into account embedded array S1X60000 series epson 247 design guide z z z z checksheet (1) have you prepared an outline drawing of the circuit blocks? yes/no (2) have you specified the cells for memory bist in the circuit? yes/no (3) have you integrated memory clocks into one line for the purpose of bist? yes/no (however, this is not an essential requirement.) (4) have you multiplexed clocks for multi-port memory for the purpose of bist? yes/no (5) sram information memory type instance name of memory net name of memory clock * *: if you?ve integrated clocks into one line or multiplexed clocks for the purpose of bist, clearly specify the bist mode. (6) test pin information pin name external pin name, etc. bist_clk shared input pin name: clock net name:, instance name of module: mode setting: mbist_en dedicated input pin name: net name: mbist_go shared output pin name: instance name of mux: mbist_done shared output pin name: instance name of mux: chapter 10 circuit design that takes testability into account 248 epson embedded array S1X60000 series design guide z z z z explanation of the checksheet (1) outline drawing of circuit blocks prepare an outline drawing for memory clock related circuits, like the one shown in figure 10-13. ? when using separate memory clock lines (with clocks for multi-port memory used in common) ? when combining memory clocks into a single line (with clocks for multi-port memory used in common) mux *cao24* *crbf* *crbf* *crbf* sysclk1 sysclk2 sysclk3 sysclk1 sysclk2 sysclk3a sysclk3b mux *cao24* *crbf* testclk sysclk1 sysclk2 sysclk3a sysclk3b mux *cao24* mux *cao24* mux *cao24* figure 10-13 outline block diagram (2) circuit description in the design of a circuit, specify the dedicated memory bist pins and multiplexers for shared pins in the rtl or netlist. at this time, make sure the dedicated input pins have their outputs written as ?open,? and that the dedicated output pins have their inputs written as ?pull-down.? similarly, make sure the multiplexers for shared pins have their select signal written as ?mbist_en? and their inputs on the bist side written as ?pull-down.? figure 10-14 shows an image of a circuit description. chapter 10 circuit design that takes testability into account embedded array S1X60000 series epson 249 design guide ? when mbist_en, mbist_go, and mbist_done are used as dedicated pins mbist_done mbist_go mbist_en buffer input buffer output buffer output imbist_en ? when mbist_en is used as a dedicated pin and mbist_go and mbist_done are used as shared pins mbist_done mbist_go mbist_en buffer input buffer output imbist_en mux mux buffer output figure 10-14 image of a circuit description (3) memory clocks integrated into one line for the purpose of bist if the circuit uses multiple memory clocks and is configured so as to integrate those clocks into one line for operation in memory bist mode, please notify epson to that effect. in addition, provide detailed information on it in (5) and (6) below. (4) clocks for multi-port memory multiplexed for the purpose of bist if the circuit has multi-port memory, it is necessary that clocks for the respective ports be equal; otherwise, the clocks must be multiplexed for operation in memory bist mode. if you?ve multiplexed these clocks, please notify epson to that effect. in addition, provide detailed information on it in (5) and (6) below. (5) sram information provide information on the sram as shown in the checksheet description examples below. (6) test pin information provide information on the test pin as shown in the checksheet description example below. chapter 10 circuit design that takes testability into account 250 epson embedded array S1X60000 series design guide z z z z checksheet description example 1: memory clocks integrated into one line (multi port memory clocks multiplexed) (1) have you prepared an outline drawing of the circuit blocks? yes/no (2) have you specified the cells for memory bist in the circuit? yes/no (3) have you integrated memory clocks into one line for the purpose of bist? yes/no (however, this is not an essential requirement.) (4) have you multiplexed clocks for multi-port memory for the purpose of bist? yes/no (5) sram information memory type instance name of memory net name of memory clock* 1 port 1024 words x 8 bits top.sys1.sram1 sysclk1 1 port 1024 words x 8 bits top.sys1.sram2 sysclk1 1 port 1024 words x 8 bits top.sys2.sram3 sysclk2 1 port 1024 words x 8 bits top.sys2.sram4 sysclk2 dual-port 512 words x 16 bits top.sys3.sram5 sysclk3a sysclk3b *: if you?ve integrated clocks into one line or multiplexed clocks for the purpose of bist, clearly specify the bist mode. (6) test pin information pin name external pin name, etc. bist_clk shared-input-pin name: testclk clock net name: sysclk1; instance name of module: sys1 clock net name: sysclk2; instance name of module: sys2 clock net name: sysclk3a and sysclk3b; instance name of module: sys3 mode setting: test = 1, mbist_en = 1, with clocks integrated into one and multiplexed mbist_en dedicated input pin name: mbist_enable net name: imbist_en mbist_go shared output pin name: signal1 instance name of mux: go_mux mbist_done shared output pin name: signal2 instance name of mux: done_mux z z z z checksheet description example 2: memory clocks not integrated into one (multi port memory clocks multiplexed) (1) have you prepared an outline drawing of the circuit blocks? yes/no (2) have you specified the cells for memory bist in the circuit? yes/no (3) have you integrated memory clocks into one line for the purpose of bist? yes/no (however, this is not an essential requirement.) (4) have you multiplexed clocks for multi-port memory for the purpose of bist? yes/no chapter 10 circuit design that takes testability into account embedded array S1X60000 series epson 251 design guide (5) sram information memory type instance name of memory net name of memory clock* 1 port 1024 words x 8 bits top.sys1.sram1 sysclk1 1 port 1024 words x 8 bits top.sys1.sram2 sysclk1 1 port 1024 words x 8 bits top.sys2.sram3 sysclk2 1 port 1024 words x 8 bits top.sys2.sram4 sysclk2 dual-port 512 words x 16 bits top.sys3.sram5 sysclk3a sysclk3b *: if you?ve integrated clocks into one line or multiplexed clocks for the purpose of bist, clearly specify the bist mode. (6) test-pin information pin name external pin name, etc. shared input pin name: sysclk1 clock net name: sysclk1; instance name of module: sys1 mode setting: none shared input pin name: sysclk2 clock net name: sysclk2; instance name of module: sys2 mode setting: none bist_clk shared input pin name: sysclk3 clock net name: sysclk3a, sysclk3b; instance name of module: sys3 mode setting: mbist_en = 1, with clocks multiplexed mbist_en dedicated input pin name: mbist_enable net name: imbist_en shared input pin name: signal1 instance name of mux: go_mux1 shared input pin name: signal2 instance name of mux: go_mux2 mbist_go shared input pin name: signal3 instance name of mux: go_mux3 shared input pin name: signal4 instance name of mux: done_mux1 shared input pin name: signal5 instance name of mux: done_mux2 mbist_done shared input pin name: signal6 instance name of mux: done_mux3 chapter 10 circuit design that takes testability into account 252 epson embedded array S1X60000 series design guide 10.6 function cell test circuits if function cells are used, a huge number of test patterns and a large amount of time are needed to confirm the operation of the entire circuit (including the customer?s circuit). for this reason, customers are requested, as in the case of ram, to design a test circuit so as to enable the function cells and the user circuit to be operated singly for the confirmation of circuit operation. please take the notes described below into consideration in the design of a test circuit. for more information, consult the function cell design guide. 10.6.1 test circuit structures (1) add a test circuit so as to enable the function cells to be individually separated from the user circuit and measurements to be taken for each block, with the pins of the function cells led out to the ic?s external pins. (2) even when inputs for the function cells are fixed to v ss or v dd , install a test circuit to allow inputs for testing. (3) even when the output pins of the function cells are unused, install a test circuit to enable all outputs of the function cells to be observed from the ic?s external pins. (4) do not combine the multiple output or input pins of the function cells for use as a single test shared pin. (5) do not use a sequential circuit in the test circuit you are generating to test the function cells. (6) do not invert the input signals from the test input pins before they are supplied to the function cells. nor can the output signals of the function cells be inverted before they are forwarded to the test output pins. (7) if the input and output pins of the function cells are led out directly, as with the ic?s pins, there is no need to install a test circuit. 10.6.2 test patterns broadly classified, the following are the three types of test patterns: 1) test patterns for testing only the user circuit 2) test patterns for testing the entire circuit 3) test patterns for testing only the function cells of these test patterns, customers are requested to generate test patterns 1) and 2). it is not necessary for customers to generate test patterns 3). existing test patterns at epson will be used. note, however, that the function cell test patterns (epson?s test patterns) cannot be used by customers. chapter 10 circuit design that takes testability into account embedded array S1X60000 series epson 253 design guide 10.6.3 test circuit data this information is required when the function cells are tested during simulation and shipping inspection. please provide epson with the following information on your test circuit. (1) clearly specify which pins of the ic are connected to which function cell pins in test mode. (2) if the test circuit is configured so as to enable multiple function cells to be tested on a single test pin, clearly specify the relationship between test modes and the function cell names selected. (3) in particular, if multiple instances of the same function cell are used, assign the function cell names in the drawing serial numbers and clearly specify which function cells are connected to the test pin. (4) clearly specify how the circuit can be switched to test mode. if function cells are used in your circuit, be sure to consult the function cell design guide in addition to this manual. chapter 10 circuit design that takes testability into account 254 epson embedded array S1X60000 series design guide 10.7 scan design to prevent defective products from becoming mixed into the market, devices must be tested using test patterns that activate logic for testing. for large designs, however, this test method requires a huge number of man-hours. scan design provides one means of solving this problem. when generating test patterns with increased fault detection rates, it is helpful to base design on certain rules and the execution of atpg (auto test pattern generation). this chapter describes the design rules to be followed in order to make the circuit suitable for scan testing (hereinafter referred to as ?scan?) and to use the atpg service from epson. because the implementation of scan is greatly affected by the design configuration, it is important to follow these rules from the beginning in the design of a circuit. if any design contrary to these rules is included, the purposes of atpg may be impaired and customers may therefore be unable to use this service. 10.7.1 about the scan circuit all registers (d-ffs, jk-ffs) included in your design are converted to scan type registers in order to create a scan path (full scan design). then, through the use of this design, atpg (auto test pattern generation) is executed. this helps to generate test patterns featuring a high fault detection rate. note: the test patterns generated by atpg are not intended for the verification of design specifications. transparent latches are not scanned. combination circuit : scan-type registers scan out scan in combination circuit figure 10-15 example of a scan circuit chapter 10 circuit design that takes testability into account embedded array S1X60000 series epson 255 design guide 10.7.2 scan design flow the following shows the design flow in cases in which the circuit is scanned and atpg is executed at epson. to scan the circuit or execute atpg yourself, consult the sales division of epson. circuit design (synchronized design) check design rules (snrc) check scan rules (checksheet) ng ng yes yes generate full scan circuit scanned netlist test pattern verification fault detection rate p&r the following must be provided to epson: y gate-level netlist y scan design checksheet (attached at the end of this chapter) y clock tree synthesis checksheet (refer to section 9.3, "clock tree synthesis.") if a previously scan circuit is to be interfaced to epson, consult epson in advance. synchronized design is recommended. unless scan rules are taken into consideration, the scan service cannot be used. the basic elements of asic design are checked using the design rule checker "snrc," which is included with the epson design kit epits. make sure the design rules for scan described in the next section are observed in your design. customers epson scan is implemented and atpg is executed. the generated netlists and test patterns are verified. the test patterns that have been confirmed as being good are used in shipping inspection. figure 10-16 scan design flow chapter 10 circuit design that takes testability into account 256 epson embedded array S1X60000 series design guide 10.7.3 design rules the following section describes the design rules to be followed in order for the scan service to be used. if the desired fault detection rate is 90% or higher, make sure all of the contents described herein are reflected in your design. in addition, when interfacing your design to epson, make sure it is accompanied by the scan design checksheet scan design checksheet scan design checksheet scan design checksheet attached at the end of this chapter. a. a. a. a. scan external pins scan external pins scan external pins scan external pins for the circuit to be scanned, all of the external pins described below are required. ? scan enable input pin (scanen) [dedicated pin] this dedicated external input pin selects between the ordinary data path (parallel operation) and the scan path (shift operation). it cannot be shared with ordinary functions or other mode functions. provide an input cell and external pin in the design for use as a dedicated external pin. ? scan data input pins [shareable] these external input pins are used to set data in the scan registers that have been incorporated into the design by scan. there must be several instances of these input pins corresponding to the number of scan registers. prepare one input pin for every 300 to 500 scan registers. as many of these input pins as the number of scan-data output pins are required. these pins may be shared with external input pins that are used in normal operation. however, clock pins, asynchronous set/reset pins, and analog signal input pins cannot be used. note that if any pin is shared, fan-out in its net increases. avoid sharing pins for critical paths. the scan data input pins are connected to the external pins at epson during scan of the design. please specify the external input pin names that can be used for this connection. unless specified, pin assignments will be made by epson. ? scan data output pins [shareable] these external output pins are used to output the observation data from the scan registers that have been incorporated into the design by scan. there must be several instances of these output pins corresponding to the number of scan registers. prepare one output pin for every 300 to 500 scan registers. as many of these output pins as the number of scan-data input pins are required. these pins may be shared with external output pins that are used in normal operation (two-state output pins are recommended). however, analog signal output pins cannot be used. note that if any pin is shared, the number of cell stages in its net increases. avoid sharing pins for critical paths. the scan-data output pins are connected to the external pins at epson when the design is scanned. please specify the external output-pin names that can be used for this connection. unless specified, pin assignments will be made by epson. ? scan clock input pin [same as an ordinary clock or dedicated pin] this clock input pin is used in the test patterns generated by atpg. because epson scan cells employ the mux scan type, this clock input pin must generally be the same system clock used in normal operation. however, if an internally generated clock exists, a dedicated clock pin for scan use may be required. for details, refer to paragraph b, ?clock design,? discussed later in this section. chapter 10 circuit design that takes testability into account embedded array S1X60000 series epson 257 design guide ? atpg enable input pin (atpgen) [dedicated pin] this external input pin activates atpg run mode. if any design exists that requires that the state be fixed, or for the outputs of blocks (including those that become black boxes during simulation), functional macros, and ram cells for which the internal logic becomes unstable, this pin must be used to fix (determine) the values. unless this procedure is used, the fault detection rate decreases considerably. prepare this external input pin as a dedicated pin. b. b. b. b. clock design clock design clock design clock design for the circuit to be scanned, clock design is very important. if the clock design is complicated, not only is the fault detection rate reduced, but the generated test pattern also becomes unstable. in such a case, the intended purposes of scan and atpg cannot be achieved. therefore, we basically recommend synchronized design. follow the rules described below in the design of a clock. keep in mind, as well, that the clock lines require optimization by cts (clock tree synthesis). for details, refer to section 9.3, ?clock tree synthesis.? ? directly control directly control directly control directly controllable structure from the outside lable structure from the outside lable structure from the outside lable structure from the outside [essential] the scan clock must propagate from an external input pin to the internal registers without being distorted in the clock waveform. although it does not matter whether an internally generated clock is present during normal operation, there must logically be no internally generated clocks in atpg run mode. examples are shown in figures 10-17 through 10-20. ideal clock ideal clock ideal clock ideal clock shown in figure 10-17 is an example of an ideal clock design. if the circuit is designed from the beginning in such a way that the clock for all registers is supplied from an external input pin as in this case, processing the clock lines by cts makes it unnecessary to correct them for purposes of scan design. because clock line corrections affect the timing of the entire circuit, it is important to take scan design into consideration from the beginning of your design work. clock figure 10-17 ideal clock processing of internally generated clocks 1 processing of internally generated clocks 1 processing of internally generated clocks 1 processing of internally generated clocks 1 if an internally generated clock is used, insert a circuit that bypasses the clock generating part (see figure 10-18) and employ a design that applies cts processing to atpg run mode. however, employment of this processing requires caution, as mux cells are added to the clock lines in that processing, which may make it difficult to adjust the timing with the clocks used for other circuit blocks. chapter 10 circuit design that takes testability into account 258 epson embedded array S1X60000 series design guide clock ? ? ? clock atpgen ? atpg mode :atpgen=1 cts special cell crbf figure 10-18 processing of internally generated clocks processing of internally generated clocks 2 (treatment of clock gating) processing of internally generated clocks 2 (treatment of clock gating) processing of internally generated clocks 2 (treatment of clock gating) processing of internally generated clocks 2 (treatment of clock gating) to avoid adding cells to the clock line for an internally generated clock, there is a method for controlling the enable line by which the clock signal is gated. an example is shown in figure 10-19. adoption of this method eliminates the need for mux cells placed in the clock line as in figure 10-18, and therefore helps create a design with relatively small clock skew. clock clock atpgen crbf atpg mode :atpgen=1 cts special cell figure 10-19 treatment of clock gating relationship between multiple clock groups relationship between multiple clock groups relationship between multiple clock groups relationship between multiple clock groups for a design with multiple clock blocks including internally generated clocks, the usable treatment method may be limited, depending on the relationship between those clock blocks. unless the circuit blocks using different clocks are physically interconnected, there will be no problems. however, caution must be exercised if for reasons of design specification they comprise either a false path (although physically connected, there is no logical communication during normal operation, or timing is not taken into consideration during logic synthesis) or a multi-cycle path (asynchronously communicating, with several latch misses tolerated). clock a b c clock generator figure 10-20 (a) example with multiple internally generated clocks chapter 10 circuit design that takes testability into account embedded array S1X60000 series epson 259 design guide shown in figure 10-20 (b) is an example of a corrective measure that can be taken in cases in which blocks a, b, and c are not physically interconnected. because there are no physical connections, clocks can be processed collectively without causing a timing problem. if clock skews in each group are resolved by cts, timing during atpg run will be stabilized. clock a b c atpgen atpg mode :atpgen=1 cts special cell crbf clock generator figure 10-20 (b) example of a corrective measure for multiple internally generated clocks 1 (when blocks are not interconnected) * assumed in this example is a method that helps to efficiently create the scan chain by applying cts processing to three clocks collectively. however, if the blocks are physically connected, though there may be no problems from a specification perspective, corrective measures for atpg must be taken. figure 10-20 (c) shows an example of treatment in such a case. because atpg generates test patterns at random, they may cause an operation in which signals are communicated via a false path that is nonexistent in the specification. in such a case, the timings associated with the data paths between blocks a, b, and c cannot be guaranteed. therefore, to ensure that the timings will be controlled for each internally generated clock, bypass these clocks on a one for one basis to external pins. in addition, we recommend the use of dedicated pins for these bypass clock pins. if the use of shared pins is unavoidable, the clock signals entering from those shared pins must be gated to prevent them from propagating to other than the registers (see figure 10-20 (d)). in such a case, because the values of those nets are fixed, the fault-detection rate decreases. clock atpgen atpg mode :atpgen=1 cts special cell scanclk2 scanclk3 clock generator a b c crbf crbf crbf scanclk1 figure 10-20 (c) example of a corrective measure for multiple internally generated clocks 2 (when blocks are interconnected) chapter 10 circuit design that takes testability into account 260 epson embedded array S1X60000 series design guide input atpgen scanclock to scan ffs figure 10-20 (d) example of scan-clock processing using shared pins ? as few clock lines as possible as few clock lines as possible as few clock lines as possible as few clock lines as possible [recommended] if multiple clocks exist as in the above case, the amount of work to be performed by customers will increase, such as due to the need to change or add a design or an increase in the number of timing reverification items. furthermore, the presence of multiple clocks may cause the length of test patterns to increase or the fault detection rate to drop. reduce the number of clock blocks as much as possible in design. this should help increase the efficiency of work when testing is conducted later. ? minimized c minimized c minimized c minimized coexistence of rising and falling edges of a clock oexistence of rising and falling edges of a clock oexistence of rising and falling edges of a clock oexistence of rising and falling edges of a clock [recommended] if both rising and falling edges are used in each clock, the efficiency of scan operation and atpg run may decrease. in some cases, the fault detection rate may drop. we recommend that scan clocks be designed using only one edge as much as possible. ? completely separated scan completely separated scan completely separated scan completely separated scan clock signals and data signals clock signals and data signals clock signals and data signals clock signals and data signals [recommended] make sure the scan clock signals and data signals are completely separated. if the scan-clock signals affect the data lines, clock signals and data signals cannot be controlled independently of each other, and faults therefore cannot be detected. c. c. c. c. asynchronous set/reset signals of registers [essential] asynchronous set/reset signals of registers [essential] asynchronous set/reset signals of registers [essential] asynchronous set/reset signals of registers [essential] a circuit is recommended in which the asynchronous set/reset signals for the flip-flops and transparent latch cells can all be controlled directly from the outside. when asynchronous set/reset signals internally generated in the design are used, take the following into consideration: ? the signals cannot be asserted (= made active) for at least the period for which scanning remains enabled. ? when internally generated asynchronous set/reset signals are used, make sure they are fed directly from the flip-flop outputs without being routed via combinational circuits, to ensure that minimum pulses will not occur. if signals routed via combinational circuits are used, take the appropriate corrective measure by, for example, using gray code. * unless such a corrective measure is taken, problems such as reduced fault detection rates or unstable test patterns may occur. chapter 10 circuit design that takes testability into account embedded array S1X60000 series epson 261 design guide d. d. d. d. handling of transparent latches [recommended] handling of transparent latches [recommended] handling of transparent latches [recommended] handling of transparent latches [recommended] transparent latches are not converted into scan cells. avoid using transparent latches as much as possible, as they are detrimental to improving the fault detection rate. when transparent latches are used, take the following into consideration: ? for the clock signals, take corrective measures similar to those discussed in paragraph b, ?clock design.? ? make sure the off-state levels of the transparent latches match those of other registers connected to the same clock line. example: through at the low level when the ff is for a rise operation (return to zero), or through at the high level when the ff is for a fall operation (return to one) however, if the scan clock is active on either edge or multiple instances of the scan clock exist, no improvements can be expected, depending on the design configuration. in such a case, take the corrective measure described below. ? if the above two points cannot be taken into consideration in your design, make sure the latches are fixed to the through state in atpg run mode. at this time, care must be taken to avoid creating a feedback loop. * unless these corrective measures are taken, problems such as reduced fault-detection rates or unstable test patterns may occur. e. e. e. e. unusable cells or design [essential] unusable cells or design [essential] unusable cells or design [essential] unusable cells or design [essential] in scan design, use of the cells specified below is inhibited. chapter 10 circuit design that takes testability into account 262 epson embedded array S1X60000 series design guide f. f. f. f. when using functional macros or ram cells [recommended] when using functional macros or ram cells [recommended] when using functional macros or ram cells [recommended] when using functional macros or ram cells [recommended] because in atpg functional macros and ram cells are handled as black boxes, it is impossible to observe the stages preceding the macros and control those following the macros. therefore, the fault detection rate is reduced considerably. to counteract this, we recommend inserting scanable flip-flops in locations immediately preceding and following the macro cells. this will bring about a significant improvement when the circuit is tested later (figure 10-21 (a)). if this is impossible from a specification standpoint, add a mode in which the macros are bypassed and configure a circuit by which the output level can be fixed (figure 10-21 (b)). macro clock macro atpgen atpg mode :atpgen=1 (a) (b) figure 10-21 example of macro cell processing g. g. g. g. internal bus [recommended] internal bus [recommended] internal bus [recommended] internal bus [recommended] do not use bus circuits comprised of internal 3-state cells. rather, we recommend that the circuit be designed using selector logic. when using said bus circuits, make sure they are fixed in such a way that the bus lines are not switched over and only one line is activated in atpg run mode. (if bus circuits are used, the fault detection rate decreases, as such circuits have fixed values.) h. h. h. h. external cells with various controls external cells with various controls external cells with various controls external cells with various controls [essential] [essential] [essential] [essential] some types of external input and external bi-directional cells available in the S1X60000 series come equipped with various control pins. these pins must be fixed using the atpg enable input pin. follow the procedure described below to process these pins. ? gating signal (c pin) fix this pin to the through state using the atpg enable input pin (atpgen). (c = 1 when atpgen = active) i. i. i. i. other other other other ? approximately 7 days are required for scan work (scan insertion to verification) at epson after netlists created in accordance with the design rules are received. ? in scan design, optimization by cts is essential. please make sure the clock tree clock tree clock tree clock tree synthesis checksheet synthesis checksheet synthesis checksheet synthesis checksheet attached in section 9.3, ?clock tree synthesis,? section 9.3, ?clock tree synthesis,? section 9.3, ?clock tree synthesis,? section 9.3, ?clock tree synthesis,? is included with the netlists presented to epson. chapter 10 circuit design that takes testability into account embedded array S1X60000 series epson 263 design guide scan design checksheet (1/2) this checksheet includes the contents we would like you to confirm before using scan or atpg services from epson. fill out this checksheet and present it to epson. without this checksheet, scan and atpg services cannot be used. information on scan design and the results of the design check are provided below. date filled in: ________ (month) _________ (day) 200_____ company name: _________________________________________ your name: _________________________________________ z z z z design information design information design information design information ? top block name: _________________________ ? desired fault-detection rate: % z z z z pin information pin information pin information pin information ? atpg enable pin names and active edges (rise/fall) pin name 1: ______________________ (rise/fall) pin name 2: ______________________ (rise/fall) pin name 3: ______________________ (rise/fall) ? scan enable pin names and active levels (high/low) pin name 1: ______________________ (high/low) pin name 2: ______________________ (high/low) pin name 3: ______________________ (high/low) ? scan clock input pin names and active levels (high/low) pin name 1: ______________________ (high/low) pin name 2: ______________________ (high/low) pin name 3: ______________________ (high/low) ? scan data input pin name pin name: _______________________________________________________ ? scan data output pin name pin name: _______________________________________________________ ? asynchronous set/reset pin names and active levels (high/low) pin name 1: ______________________ (high/low) pin name 2: ______________________ (high/low) pin name 3: ______________________ (high/low) chapter 10 circuit design that takes testability into account 264 epson embedded array S1X60000 series design guide scan design checksheet (2/2) z z z z check items (mark the applicable items with a check.) check items (mark the applicable items with a check.) check items (mark the applicable items with a check.) check items (mark the applicable items with a check.) ? ? the scan clock pins have been treated in accordance with the design rules described in section 10.7.3, paragraph b. ? ? asynchronous set/reset signals of registers have been treated in accordance with the design rules described in section 10.7.3, paragraph c. ? transparent latches (select one of the following.) ? not used ? treated in accordance with section 10.7.3, paragraph d ? not treated in accordance with section 10.7.3, paragraph d. a reduction in the fault-detection rate is acknowledged. ? other: ____________________________________________________________________ ? ? cells or circuits the use of which is inhibited as described in section 10.7.3, paragraph e, do not exist. ? functional macros or ram cells (select one of the following.) ? not used ? treated in accordance with section 10.7.3, paragraph f ? not treated in accordance with section 10.7.3, paragraph f. a reduction in the fault detection rate is acknowledged. ? other: ____________________________________________________________________ ? internal 3-state bus (select one of the following.) ? not used ? treated in accordance with section 10.7.3, paragraph g ? not treated in accordance with section 10.7.3, paragraph g. a reduction in the fault-detection rate is acknowledged. ? other: ____________________________________________________________________ ? external cells with various control pins (select one of the following.) ? not used ? treated in accordance with section 10.7.3, paragraph h ? not treated in accordance with section 10.7.3, paragraph h. a reduction in the fault detection rate is acknowledged. ? other: ____________________________________________________________________ ? other ______________________________________________________________________________ ______________________________________________________________________________ ______________________________________________________________________________ chapter 10 circuit design that takes testability into account embedded array S1X60000 series epson 265 design guide 10.8 boundary scan design a boundary scan (jtag) insertion service is available from epson. when this service is used, an ieee1149.1 compliant boundary scan circuit and a control circuit (tap controller) are inserted in the periphery of the logic circuit. at the same time, bsdl files that contain information on those circuits are presented to customers. because the inserted boundary scan function patterns are created by epson, it is not necessary for customers to create patterns for the boundary scan circuit. 10.8.1 boundary scan design flow circuit design check design rules (snrc) check rules (checksheet) yes yes insert boundary scan generate test pattern and bsdl for confirmation of boundary scan circuit boundary scan inserted netlist bsdl verification the following must be presented to epson: y gate level netlist y design information sheet (attached at the end of this section) the basic elements of asic design are checked using the design rule checker "snrc" included with the epson design kit, epits. please conduct a check to confirm that the design rules for boundary scan described in the next section are observed in your design. customers epson the generated netlists and test patterns are verified. the test patterns that have been confirmed to be good are used in shipping inspection. test pattern to customers figure 10-22 boundary scan design flow chapter 10 circuit design that takes testability into account 266 epson embedded array S1X60000 series design guide 10.8.2 instructions the jtag instructions specified below are supported. table 10-4 supported instruction codes instruction code sample/preload 0...10 bypass 1...11 extest 0...00 clamp selectable as desired (*1) highz selectable as desired (*1) idcode 0...01 note *1: unless explicitly specified, epson will select the appropriate code. no duplicate codes can be specified. instruction bit sizes may be selected in the range of 2 to 32 bits. unless explicitly specified, epson will determine the appropriate instruction size. 10.8.3 estimating the number of gates the extent of the increase in the number of gates as a result of boundary scan insertion depends on the asic series used and the instructions and bit sizes supported. estimate the approximate number of gates using the information given below. table 10-5 gate count estimation (sog equivalent) boundary scan block gate counts tap controllers + miscellaneous gates approx. 1000 (bcs) input pin when using normal cells: approx. 30 (bc/pin) when using dedicated observation cells: approx. 15 (bc/pin) 2-state output pin approx. 35 (bc/pin) 3-state output pin approx. 65 (bc/pin) bi-directional pin approx. 95 (bc/pin) 10.8.4 design rules for the boundary scan service to be used, it is necessary that customers? logic circuits be designed in observance of the restrictions described below. before releasing data to epson, please be sure to confirm the circuit information using the boundary scan checksheet boundary scan checksheet boundary scan checksheet boundary scan checksheet attached at the end of this chapter, and to fill out and present the design information sheet to epson. please note that if any circuit violating the restrictions exists, this service cannot be used. a. a. a. a. coexistence with dc/ac easy coexistence with dc/ac easy coexistence with dc/ac easy coexistence with dc/ac easy to to to to test circuits inhibited test circuits inhibited test circuits inhibited test circuits inhibited coexistence with the easy to test circuits described in section 10.3, ?test circuit which section 10.3, ?test circuit which section 10.3, ?test circuit which section 10.3, ?test circuit which simplifies dc an simplifies dc an simplifies dc an simplifies dc and ac testing,? d ac testing,? d ac testing,? d ac testing,? is inhibited. to be suitable for the boundary scan service, a design cannot have dc/ac easy to test circuits inserted in it. chapter 10 circuit design that takes testability into account embedded array S1X60000 series epson 267 design guide b. b. b. b. character strings usable for external pins character strings usable for external pins character strings usable for external pins character strings usable for external pins due to the rules for the bsdl file format, external pin names are subject to the following limitations: ? only alphanumeric characters (a to z, a to z, 0 to 9) and the underscore (_) can be used. ? the characters are not case-sensitive (for example, clk and clk are assumed to be the same). ? the first character must always be a letter (for example, 0clk and _clk are not accepted). ? the underscore cannot be used in succession (for example, sys__clk is not accepted). ? the character string cannot end with an underscore (for example, clk_ is not accepted). c. c. c. c. preparation of de preparation of de preparation of de preparation of dedicated external pins dicated external pins dicated external pins dicated external pins the boundary scan circuit always requires five dedicated external pins. insert these external pins in your design in accordance with the rules described below. ? clock (tck) this is a clock pin for the boundary scan circuit. prepare an input cell and confirm that its output port is not connected. ? mode select (tms) this is a mode select pin for the boundary scan circuit. prepare an input cell and confirm that its output port is not connected. for this input cell, use an input cell with pull-up. ? data input (tdi) this is a scan data input pin for the boundary scan circuit. prepare an input cell and confirm that its output port is not connected. for this input cell, use one with pull-up. ? data output (tdo) this is a scan data output pin for the boundary scan circuit. use a 3-state output cell and confirm that its input port is tied low to gnd. ? reset (trst) this is an asynchronous reset pin for the boundary scan circuit. prepare an input cell and confirm that its output port is not connected. for this input cell, use one with pull-up. ibc u1 ( .pad(tck) ); // ibc: normal input cell ibcp1 u2 ( .pad(tms) ); // ibcp1: input cell with pull-up ibcp1 u3 ( .pad(tdi) ); ibcp1 u4 ( .pad(trst) ); tb1 u5 ( .pad(tdo), .a(1?b0), .e(1?b0) ); // tb1: 3-state output cell figure 10-23 example of dedicated pin description (written in verilog) chapter 10 circuit design that takes testability into account 268 epson embedded array S1X60000 series design guide d. d. d. d. regarding hierarchical blocks regarding hierarchical blocks regarding hierarchical blocks regarding hierarchical blocks make sure the hierarchical blocks in the netlist are configured as shown below. note that, following boundary scan insertion, hierarchical blocks such as a tap controller are added. ? place i/o cells in the top block. ? place other logic cells in a sub-block one layer below that as much as possible. figure 10-24 image of a hierarchical block configuration e. e. e. e. regarding i/o regarding i/o regarding i/o regarding i/o cell types cell types cell types cell types if the design includes one of the following types of i/o cells, the boundary scan service cannot be used: ? i/o cells with test mode ? gated input cells ? open drain output cells ? i/o cells with pull-up/pull-down registor f. f. f. f. external pins handling analog signals external pins handling analog signals external pins handling analog signals external pins handling analog signals boundary scan cells are not inserted for oscillation circuit input/output pins or external pins that handle analog signals. g. g. g. g. multibonding and multipads multibonding and multipads multibonding and multipads multibonding and multipads if the design includes multibonding or multipads, the boundary scan service cannot be used. i/o cell user logic blocks including bsr tap controller chapter 10 circuit design that takes testability into account embedded array S1X60000 series epson 269 design guide boundary scan checksheet please confirm the check items listed below before interfacing to epson, and present the design information sheet shown on the next page to epson. please note that if any circuit violating these check items exists or any information is omitted, the boundary scan service cannot be used. please confirm the following items before presenting netlists to epson: (a) the supported range of instructions complies with table 10-4. (b) the circuits described in section 10.3, ?test circuit which simplifies dc and ac testing,? cannot coexist. (c) confirm that the external pin names comply with section 10.8.4, paragraph b ?character strings usable for external pins.? (d) regarding dedicated pins (i) conduct a check to confirm that five dedicated pins already exist in the netlist. (ii) for the tms, tdi, and trst equivalent pins, use input cells with pull-ups. (iii) for the tdo equivalent pin, use a 3-state output cell. (iv) conduct a check to confirm that the dedicated pins are not shared with any other functions. (e) place i/o cells in the top layer. (f) do not use the i/o cells listed in section 10.8.4, paragraph e. (g) boundary scan cells cannot be inserted for oscillation circuit input/output pins or external pins that handle analog signals. (h) conduct a check to confirm that multibonding and multipads are not used. chapter 10 circuit design that takes testability into account 270 epson embedded array S1X60000 series design guide design information sheet (fill out this sheet and present it to epson by the time the design is released.) information on boundary scan design is provided below. date filled in: ________ (month) _________ (day) 200____ company name: ______________________________________ your name: __________________________________________ z z z z design information design information design information design information ? top block name: _______________ 1. desired instructions (select the desired instructions.) ? essential instructions ? clamp instructions ? highz instructions ? idcode instructions codes comply with table 10-4. your desired code ____________ (*1) your desired code ____________ (*1) codes comply with table 10-4. 2. instruction bit size (select the desired size.) ? not specified ? specified determined by epson bit size ____________ bits(*2) 3. selection of boundary scan cells to choose the boundary scan cells to be inserted, supply the information specified below. unless explicitly specified, the following will be applied at epson: ? dedicated observation cells may be used, if necessary, for the system clock or asynchronous reset bits. ? boundary scan cells will not be inserted for input and output pins handling analog signals. ? external pin names for which dedicated observation cells are used ______________________________________________________________________________ ? external pin names for which boundary scan cells are not to be inserted ______________________________________________________________________________ ? other ______________________________________________________________________________ ? dedicated pin information (enter the pin names corresponding to each pin.) tck: _________ tms: _________ tdi: __________ tdo: _________ trst: _________ ? user circuit information system clock name: ______________________________________________________ asynchronous reset signal name: ______________________________________________________ top block name: ______________________________________________________ sub block name(*3): ______________________________________________________ notes *1 do not select duplicate codes for any instruction. unless explicitly specified, codes will be assigned by epson. in addition, make sure the bit size matches that in item 2, ?instruction bit size.? *2 bit sizes can be specified in the range of 2 to 32 bits. *3 enter all sub blocks that exist immediately below the top block. if any buffers or delay elements inserted for delay adjustment or the like exist in the top block, enter their instance names. chapter 11 test pattern generation embedded array S1X60000 series epson 271 design guide chapter 11 test pattern generation the test patterns received from customers to confirm ic specifications are not subject to many restrictions. basically, any test patterns may be accepted when completed by a reasonable deadline and can be simulated individually with the ic alone. (for details, contact epson.) for the shipping test, however, some restrictions are imposed depending on tester capability. test patterns for the shipping test will be created from those received from customers to confirm ic specifications by modifying the patterns at epson. therefore, please consider the following restrictions when creating test patterns to confirm ic specifications. 11.1 testability consideration because test patterns are used for the shipping inspection of a product, they must be generated so as to enable the entire internal circuit of the lsi to be tested. if the lsi?s internal circuit contains any untested part, there is a possibility of a defective product being shipped, as that part of the product cannot be tested during the shipping inspection. generally speaking, the entire internal circuit of the lsi cannot be tested easily. therefore, it is important that the testability of the lsi be taken into consideration from the beginning of circuit design. by inserting epson-recommended test circuits in your design, the dc testing and various other conditions required for test patterns can be set easily. for details, refer to section 10.3, ?test circuit which simplifies dc and ac testing,? in chapter 10. 11.2 usable input waveforms test patterns are normally comprised of logic 0s and 1s. however, when circuit operation is simulated or the circuit is tested using an lsi tester, the input waveform can have a delay inserted or pulses generated in it. the following two types of waveforms can be used in the creation of test patterns. ? nrz (non return to zero) normally used for signals other than the clock. this type of waveform can change state once per test period and can be given a delay. ? rz (return to zero) use this for clock signals and the like. because this type of waveform can generate a positive or negative pulse within a test period, it aids in the efficient creation of clock signals. it can be given a delay, as with nrz. test rate rz waveform output-waveform nrz waveform strobe input delay pulse width figure 11-1 limitations on timing settings chapter 11 test pattern generation 272 epson embedded array S1X60000 series design guide 11.3 constraints on test patterns this chapter describes the restrictions on test patterns for the shipping test. 11.3.1 test rate and event counts the following shows the test rate and event counts. test rate : 100 ns or more, in 1 ns increments (typ.: 200 ns) number of events per test pattern : up to 256k events number of test patterns : up to 30 patterns total number of events in test patterns: up to 1m events 11.3.2 input delay the following shows the restrictions related to input delays. (a) range of input delays the input delay must be given in the range shown below. for the constraints on strobe points, refer to section 11.3.5, ?strobes.? 0 ns input delay value < strobe point (b) phase difference in input delay if the input delay requires a phase difference, add a difference of 3 ns or more. (c) types of input delays there may be up to 8 types of input delays in one test pattern. 0 ns delays are counted as one type. input delays with different waveforms (rz or nrz) or pulse widths must also be counted as being different even when their delay values are the same. 11.3.3 pulse width the pulse width in an rz waveform must be 15 ns or more. 11.3.4 input waveform format input waveforms can take on the values 0, 1, p, or n. the values p and n represent pulse inputs in an rz waveform. furthermore, the values p and n can only be defined in a combination of (0, p) or (1, n) for the same pin in one test pattern. no other combinations can be used. for bi-directional pins, an rz waveform can be applied only when they do not have an output state in one test pattern. 11.3.5 strobes the strobe related constraints are as follows: (a) only one type of strobe can be defined in each test pattern. (b) the minimum value of the strobe must be such that in all events, at least 30 ns elapses after all output signals have changed state pursuant to the applied input signal. (c) the maximum value of the strobe must be smaller than the value of test rate ? 15 ns. (d) define the strobe in 1 ns units. chapter 11 test pattern generation embedded array S1X60000 series epson 273 design guide 11.4 notes regarding dc testing test patterns are used not only for function testing, but also for dc testing in which output voltages and the like are measured. make sure the following items of dc testing can be performed when creating test patterns. however, the test patterns described in this chapter need not be prepared when adopting those shown in chapter 10, ?circuit design that takes testability into account.? dc testing is conducted in order to verify the dc parameters of the lsi. measurements for dc testing are taken at the end of a measurement event. for this reason, the measured pins cannot have their state changed in accordance with the strobe position in the measurement event. the following items of dc parameters are measured: (a) output characteristic test (v oh , v ol ) the current drive capability of the output buffer is measured. the measured pin is driven to an output level at which measurement can be conducted, and the value of the voltage drop that occurs when the designated current load is applied to the pin is measured. for the output-characteristic test to be performed, the test pattern must contain all possible states in which the measured pins can operate. furthermore, those states must be sufficiently stable that they will not change even when the test rate is infinitely extended in the measurement event. (b) quiescent current test (i dds ) the quiescent current is the leakage current that flows in the power supplies of the lsi when its inputs are in a steady state. because the amount of this current is generally very small, it must be measured while no currents other than the leakage current are flowing. to meet this requirement, all of the conditions listed below must be satisfied. note also that the test pattern must contain at least two points of events in which the quiescent current can be measured. (1) all of the input pins shall be in a steady state. (2) a high or low level signal shall be applied to or output from the bi-directional pins. (3) no oscillating or other operating parts shall exist in the circuit. (4) the internal 3-state buffer (internal bus) shall not be left floating or have no data or signal contention. (5) the ram, rom, and megacells shall not be in a current flowing state. (6) a high level signal shall be applied to the input pins with pull-up resistors. (7) a high level signal shall be applied to or output from the bi-directional pins with pull-up resistors. (8) the bi-directional pins with pull-down resistors shall be in input mode or outputting a low-level signal. (c) input current test measurements are taken of the inputs for the input buffers. the items measured in this test are the input leakage current and the pull-up/pull-down currents. measurements in this test are performed by applying v dd or v ss level voltage to the measured pin, and then measuring the amount of current flowing in the pin. this chapter 11 test pattern generation 274 epson embedded array S1X60000 series design guide means that a high or low level voltage is applied to the measured pin during measurement. for example, if a v dd level (high level) voltage is applied to the measured pin while input for it is held low, the measured pin changes state from low to high, causing the lsi to perform an unintended operation. for the input-current test, in an event in which input for the measured pin is held high in the test pattern, measurements must be taken by applying a v dd level voltage to the measured pin, and in an event in which input for the measured pin is held low, measurement must be taken by applying a v ss level voltage to the measured pin. therefore, an input current test cannot be conducted unless the test pattern includes these states for the measured pin. the input current test is further classified as follows: (1) input-leakage-current test (i ih , i il ) measurements are taken of the input currents for the input buffers without pull-up/pull-down resistors. the current flowing in the input buffer when a high level voltage is applied to the buffer is referred to as ?i ih ,? and is guaranteed by the maximum current value. for this test to be conducted, the test pattern must include an event in which the input for the measured pin is held high. if the measured pin is a bi-directional pin, it must be in input mode and its input must be held high. the current flowing in the input buffer when a low level voltage is applied to the buffer is referred to as ?i il ,? and is guaranteed by the maximum current value. for this test to be conducted, the test pattern must include an event in which the input for the measured pin is held low. if the measured pin is a bi-directional pin, it must be in input mode and its input must be held low. (2) pull-up current test (i pu ) the current flowing in the input buffer is measured using a pull-up resistor when a low level voltage is applied to the buffer. for this test to be conducted, the test pattern must include an event in which the input for the measured pin is held low. if the measured pin is a bi-directional pin, it must be in input mode and its input must be held low. (3) pull-down current test (i pd ) the current flowing in the input buffer is measured using a pull-down resistor when a high level voltage is applied to the buffer. for this test to be conducted, the test pattern must include an event in which input for the measured pin is held high. if the measured pin is a bi-directional pin, it must be in input mode and its input must be held high. (4) off state leakage current (i oz ) measurements are taken of the leakage current flowing in the open-drain or 3-state output buffer when its output enters a high impedance state. in this test, the measured pin is placed in a high impedance state and measurements are taken of current values by applying a v dd level and v ss level voltage to the measured pin, respectively. therefore, the test pattern must include an event in which the measured pin enters a high impedance state. chapter 11 test pattern generation embedded array S1X60000 series epson 275 design guide 11.5 notes regarding the use of oscillation circuits for systems using oscillation circuits (examples shown below), in general, because the oscillation inverter?s drive capability is small and the oscillation circuit?s output waveform is affected by the load in the measurement environment, the waveform does not precisely propagate to the gates in the stages following the oscillation circuit. g e x d lin lot pad pad gate side signal enable signal g x d lin lot pad pad gate side signal drain side signal clock signal oscillation cell oscillation cell drain side signal clock signal figure 11-2 examples of oscillation circuits to reproduce the simulation state using a tester, therefore, a corrective measure is taken in which reverse drive is applied (i.e., by supplying a waveform to the drain pin that is in phase with the signal output to the drain). if the oscillation inverter is comprised of an inverter, the reverse drive signal, i.e., the signal to be entered from the drain, can be produced simply by entering a signal 180 degrees out of phase with the signal being applied to the gate. if comprised of a nand gate (known as an ?intermittent oscillator? or ?gated osc?), however, the signal to be entered cannot easily be determined from the gate signal alone. therefore, the reverse drive waveform is determined based on the expected value of the drain pin. in this method, if the input waveform is an nrz waveform and has a strobe at the end of a test period, the expected value of the drain pin can be used directly for the input waveform to produce a reverse drive waveform. in the case of an rz waveform, however, the expected value of the drain pin remains high or low regardless of whether the pin is oscillating or turned off, and a reverse drive waveform cannot be determined by referring to the expected value of the drain pin. for systems using intermittent oscillators, therefore, take the following into consideration: 1. use of an rz waveform for the input signal is inhibited. 2. the clock signal cannot have its state changed by changing the enable signal. chapter 11 test pattern generation 276 epson embedded array S1X60000 series design guide 11.6 regarding ac testing in ac testing, the elapsed time from when the state of any input pin changes until the change propagates to the output pin is measured. the measurement paths chosen by customers are used for ac testing. however, the test patterns described in this chapter need not be prepared when adopting those shown in chapter 10, ?circuit design that takes testability into account.? 11.6.1 constraints regarding measurement events ac testing is normally conducted using a test method known as the binary research method. for the measured pin (i.e., an output pin the state of which has changed), there can be only one location within the measurement event at which the measured pin changes state. (no measurements can be taken at the pins from which rz waveforms are output. nor can measurements be taken in cases in which hazards are output in the measurement event.) furthermore, the state changes of the signal that can be measured must be high to low or low to high (changes in which z is involved cannot be measured). it should also be noted that caution must be used in the selection of a measurement event in which no multiple output pins change state at the same time, or in which there is no signal contention between the bi-directional pins and the lsi tester. this is due to the fact that a simultaneous change in state or signal contention causes the lsi?s power supply to fluctuate greatly, which affects the output waveform at the measured pin, making precise measurement impossible. 11.6.2 constraints on the measurement location for ac testing limit the measurement locations in ac testing to four. 11.6.3 constraints regarding the path delay which is tested in the ac measurement path, the larger the delay, the greater the measurement accuracy. make sure the delay time in the measured path is set to 30 ns or more, but does not exceed the strobe point under max conditions of test simulation. 11.6.4 other constraints (1) do not specify paths from the oscillation circuit. (2) specify paths that do not pass through the internal 3-state circuit (internal bus). (3) do not specify paths in which there is any bi-directional cell between the input buffer and the output buffer of the measured path. (4) if power supplies with two or more voltage ranges are used, limit the measured voltage in ac testing to one of those voltage ranges. chapter 11 test pattern generation embedded array S1X60000 series epson 277 design guide 11.7 test patterns constraints for bi-directional pins due to constraints on tester performance, the bi-directional pins cannot be switched between input and output modes more than twice per event. therefore, make sure the test patterns created do not use rz waveforms to control the switching of input/output modes for the bi-directional cells. 11.8 notes on device in a high impedance state at epson, cmos devices are subject to the limitation that, when the input pins are in a high impedance state, the device operation cannot be guaranteed and the high impedance state is inhibited during simulation. to solve such high impedance related problems, i/o cells with pull-up/pull-down resistors are available from epson. however, the propagation delays in the pull-up/pull-down resistors of these cells are not taken into consideration in simulation for the reasons specified below. therefore, because operation cannot be precisely simulated, the non input state for the bi-directional pins with pull-up/pull-down resistors in input mode is also inhibited during simulation. appendix a1 electrical characteristics data (x type) 278 epson embedded array S1X60000 series design guide appendix a1 electrical characteristics data (x type) a1.1 characteristics of input/output buffers (3.3 v operation) a1.1.1 input buffer characteristics (3.3 v 0.3 v) ? standard type input buffers 4 3 2 1 123 4 v in (v) v out (v) 0 t a = 25 c hv dd = 3.6v hv dd = 3.3v hv dd = 3.0v figure a1-1 input characteristics (lvttl) 4 3 2 1 123 4 v in (v) v out (v) 0 t a = 25 c hv dd = 3.6v hv dd = 3.3v hv dd = 3.0v figure a1-2 input characteristics (cmos) 4 3 2 1 123 4 v in (v) v out (v) 0 t a = 25 c hv dd = 3.6v hv dd = 3.3v hv dd = 3.0v figure a1-3 input characteristics (pci-3 v) ? schmitt-trigger type input buffers 4 3 2 1 123 4 v in (v) v out (v) 0 t a = 25 c hv dd = 3.6v hv dd = 3.3v hv dd = 3.0v figure a1-4 input characteristics (lvttl schmitt) 4 3 2 1 123 4 v in (v) v out (v) 0 t a = 25 c hv dd = 3.6v hv dd = 3.3v hv dd = 3.0v figure a1-5 input characteristics (cmos schmitt) appendix a1 electrical characteristics data (x type) embedded array S1X60000 series epson 279 design guide a1.1.2 input through current (3.3 v 0.3 v) 0 0 200u 400u 600u 800u 1m 1.2m 1.4m 1.6m 1.8m 2m 2.2m 2.4m 2.6m hv dd /lv dd = 3.6v/2.7v 1 1.5 voltage x (lin) (volts) currents (lin) 3 3.5 2.5 2 500m figure a1-6 input through current (cmos) 0 0 200u 400u 600u 800u 1m hv dd /lv dd = 3.6v/2.7v 1 1.5 voltage x (lin) (volts) currents (lin) 33.5 2.5 2 500m figure a1-7 input through current (cmos schmitt) appendix a1 electrical characteristics data (x type) 280 epson embedded array S1X60000 series design guide 0 0 200u 400u 600u 800u 1m 1.2m 1.4m 1.6m 1.8m 2m 2.2m 2.4m 2.6m 2.8m hv dd /lv dd = 3.6v/2.7v 1 1.5 voltage x (lin) (volts) currents (lin) 3 3.5 2.5 2 500m figure a1-8 input through current (lvttl) 0 0 200u 400u 600u 800u 1m 1.2m hv dd /lv dd = 3.6v/2.7v 11.5 voltage x (lin) (volts) currents (lin) 33.5 2.5 2 500m figure a1-9 input through current (lvttl schmitt) appendix a1 electrical characteristics data (x type) embedded array S1X60000 series epson 281 design guide 0 0 200u 400u 600u 800u 1m 1.2m 1.4m 1.6m 1.8m 2m 2.2m 2.4m 2.6m 2.8m 3m hv dd /lv dd = 3.6v/2.7v 1 1.5 voltage x (lin) (volts) currents (lin) 33.5 2.5 2 500m figure a1-10 input through current (pci) appendix a1 electrical characteristics data (x type) 282 epson embedded array S1X60000 series design guide a1.1.3 output buffer characteristics (3.3 v 0.3 v) (1) list of output buffer specifications table a1-1 output current characteristics output current type number i oh *1 i ol *2 unit type s -0.1 0.1 ma type m -1 1 ma type 1 -3 3 ma type 2 -6 6 ma type 3 -12 12 ma pci confirmed to the pci standard ma note *1: v oh = hv dd -0.4 v (hv dd = 3.3 v) *2: v ol = 0.4 v (hv dd = 3.3 v) appendix a1 electrical characteristics data (x type) embedded array S1X60000 series epson 283 design guide (2) i ol -v ol and i oh -v oh z i ol -v ol 1.0 0.5 t a = 25 c 1.0 i ol (ma) v ol (v) type s 0.5 0.0 0 hv dd = 3.6v hv dd = 3.3v hv dd = 3.0v figure a1-11 10 5 t a = 25 c 1.0 i ol (ma) v ol (v) type m 0.5 0.0 0 hv dd = 3.6v hv dd = 3.3v hv dd = 3.0v figure a1-12 20 10 t a = 25 c 1.0 i ol (ma) v ol (v) type 1 0.5 0.0 0 hv dd = 3.6v hv dd = 3.3v hv dd = 3.0v figure a1-13 50 25 t a = 25 c 1.0 i ol (ma) v ol (v) type 2 0.5 0.0 0 hv dd = 3.6v hv dd = 3.3v hv dd = 3.0v figure a1-14 100 50 t a = 25 c 1.0 i ol (ma) v ol (v) type 3 0.5 0.0 0 hv dd = 3.6v hv dd = 3.3v hv dd = 3.0v figure a1-15 100 50 t a = 25 c 1.0 i ol (ma) v ol (v) pci 3v 0.5 0.0 0 hv dd = 3.6v hv dd = 3.3v hv dd = 3.0v figure a1-16 appendix a1 electrical characteristics data (x type) 284 epson embedded array S1X60000 series design guide 100 50 t a = 25 c 1.0 i ol (ma) v ol (v) type 1 to 3 0.5 0.0 0 hv dd = 3.3v type 3 ty p e 2 type 1 figure a1-17 z i oh -v oh i oh (ma) -1.0 -0.5 0.0 t a = 25 c -1.0 type s -0.5 hv dd = 3.6v hv dd = 3.3v hv dd = 3.0v output voltage v oh - supply voltage hv dd (v) figure a1-18 i oh (ma) -1.0 -0.5 0.0 t a = 25 c -1.0 type m -0.5 hv dd = 3.6v hv dd = 3.3v hv dd = 3.0v output voltage v oh - supply voltage hv dd (v) figure a1-19 i oh (ma) -20 -10 0 t a = 25 c -1.0 type 1 -0.5 0.0 hv dd = 3.6v hv dd = 3.3v hv dd = 3.0v output voltage v oh - supply voltage hv dd (v) figure a1-20 i oh (ma) -50 -25 0 t a = 25 c -1.0 type 2 -0.5 0.0 hv dd = 3.6v hv dd = 3.3v hv dd = 3.0v output voltage v oh - supply voltage hv dd (v) figure a1-21 appendix a1 electrical characteristics data (x type) embedded array S1X60000 series epson 285 design guide i oh (ma) -100 -50 0 t a = 25 c -1.0 type 3 -0.5 0.0 hv dd = 3.6v hv dd = 3.3v hv dd = 3.0v output voltage v oh - supply voltage hv dd (v) figure a1-22 i oh (ma) -100 -50 0 t a = 25 c -1.0 pci 3v -0.5 0.0 hv dd = 3.6v hv dd = 3.3v hv dd = 3.0v output voltage v oh - supply voltage hv dd (v) figure a1-23 i oh (ma) -100 -50 0 t a = 25 c -1.0 type 1 to 3 -0.5 0.0 hv dd = 3.3v type 3 type 2 type 1 output voltage v oh - supply voltage hv dd (v) figure a1-24 (3) i ol and i oh temperature characteristics 1.40 1.30 1.20 1.10 1.00 0.90 0.80 0.70 0.60 i ol (ratio) -40 -20 -60 20 040 t a ( c) 60 80 100 120 140 hv dd = 3.3v i ol = 1.0 (t a = 25 c) figure a1-25 ambient temperature (t a ) - output current (i ol ) 1.40 1.30 1.20 1.10 1.00 0.90 0.80 0.70 0.60 i oh (ratio) -40 -20 -60 20 040 t a ( c) 60 80 100 120 140 hv dd = 3.3v i oh = 1.0 (t a = 25 c) figure a1-26 ambient temperature (t a ) - output current (i oh ) appendix a1 electrical characteristics data (x type) 286 epson embedded array S1X60000 series design guide (4) output delay time vs. output load capacitance (c l ) 0 00 200 300 400 0 50 100 150 200 c l (pf) t plh (ns) hv dd = 3.3v v l = 1.65v t a = 25 c xhobmt xhobst figure a1-27 output delay time (t plh ) vs. output load capacitance (c l ) 0 00 200 300 400 0 50 100 150 200 c l (pf) t phl (ns) hv dd = 3.3v v l = 1.65v t a = 25 c xh o bmt xhobst figure a1-28 output delay time (t phl ) vs. output load capacitance (c l ) 0 5 0 5 20 0 50 100 150 200 c l (pf) t plh (ns) hv dd = 3.3v v l = 1.65v t a = 25 c xhob2t xhob3t xhobt figure a1-29 output delay time (t plh ) vs. output load capacitance (c l ) 0 5 0 5 20 0 50 100 150 200 c l (pf) t phl (ns) hv dd = 3.3v v l = 1.65v t a = 25 c xhob2t xhob3t xhob1t figure a1-30 output delay time (t phl ) vs. output load capacitance (c l ) 0 2 3 4 5 0 50 100 150 200 c l (pf) t plh (ns) hv dd = 3.3v v l = 1.65v t a = 25 c xhobpb figure a1-31 output delay time (t plh ) vs. output load capacitance (c l ) 0 2 3 4 5 0 50 100 150 200 c l (pf) t phl (ns) hv dd = 3.3v v l = 1.65v t a = 25 c xhobpbt figure a1-32 output delay time (t phl ) vs. output load capacitance (c l ) appendix a1 electrical characteristics data (x type) embedded array S1X60000 series epson 287 design guide (5) output buffer rising/falling time vs. output load capacitance (c l ) 0 200 400 600 800 0 50 100 50 200 c l (pf) t r (0%-90%) (ns) hv dd = 3.3v v l = 1.65v t a = 25 c xhobmt xhobst figure a1-33 rising time (t r ) vs. output load capacitance (c l ) 0 200 400 600 800 c l (pf) t f (0%-90%) (ns) hv dd = 3.3v v l = 1.65v t a = 25 c xhobmt xhobst 0 50 100 50 200 figure a1-34 falling time (t f ) vs. output load capacitance (c l ) 0 0 20 30 40 c l (pf) t r (0%-90%) (ns) hv dd = 3.3v v l = 1.65v t a = 25 c xhob2t xhob3t xhob1t 0 50 100 50 200 figure a1-35 rising time (t r ) vs. output load capacitance (c l ) 0 0 20 30 40 c l (pf) t f (0%-90%) (ns) hv dd = 3.3v v l = 1.65v t a = 25 c xhob2t xhob3t xhob1t 0 50 100 50 200 figure a1-36 falling time (t f ) vs. output load capacitance (c l ) 0 2 4 6 8 0 c l (pf) t r (0%-90%) (ns) xhobpbt 0 50 100 50 200 hv dd = 3.3v v l = 1.65v t a = 25 c figure a1-37 rising time (t r ) vs. output load capacitance (c l ) 0 2 4 6 8 0 c l (pf) t f (0%-90%) (ns) hv dd = 3.3v v l = 1.65v t a = 25 c xhobpbt 0 50 100 150 200 figure a1-38 falling time (t f ) vs. output load capacitance (c l ) appendix a1 electrical characteristics data (x type) 288 epson embedded array S1X60000 series design guide (6) pull-up and pull-down resistance z pull-up characteristics 2.4 hv dd (v) r plu (k ? ) 2.7 3 3.3 3.6 3.9 4.2 t a = 25 c type 1 type 2 250 200 150 100 50 0 figure a1-39 pull-up resistance (r plu ) vs. hv dd -60 -40 -20 0 20 40 60 80 100 120 140 t a ( c) r plu (k ? ) type 1 type 2 250 200 150 100 50 0 hv dd = 3.3v figure a1-40 pull-up resistance (r plu ) vs. ambient temperature z pull-down characteristics 2.4 hv dd (v) r pld (k ? ) 2.7 3 3.3 3.6 3.9 4.2 t a = 25 c type 1 type 2 250 200 150 100 50 0 figure a1-41 pull-down resistance (r pld ) vs. hv dd -60 -40 -20 0 20 40 60 80 100 120 140 t a ( c) r pld (k ? ) type 1 type 2 250 200 150 100 50 0 hv dd = 3.3v figure a1-42 pull-down resistance (r pld ) vs. ambient temperature (t a ) appendix a1 electrical characteristics data (x type) embedded array S1X60000 series epson 289 design guide (7) output waveforms z high speed type output buffer conditions: hv dd = 3.3v, t a = 25 c, c l = 15pf, i ol = 12 ma 6 4 2 0 -2 output voltage v o (v) (5 ns/div) figure a1-43 output waveform (xhob3at) z normal type output buffer conditions: hv dd = 3.3v, t a = 25 c, c l = 15pf, i ol = 12 ma 6 4 2 0 -2 output voltage v o (v) (5 ns/div) figure a1-44 output waveform (xhob3t) z low noise type output buffer conditions: hv dd = 3.3v, t a = 25 c, c l = 15pf, i ol = 12 ma 6 4 2 0 -2 output voltage v o (v) (5 ns/div) figure a1-45 output waveform (xhob3bt) appendix a1 electrical characteristics data (x type) 290 epson embedded array S1X60000 series design guide a1.2 characteristics of input/output buffers (2.5 v operation) a1.2.1 input buffer characteristics (2.5 v 0.2 v) ? standard type input buffers 4 3 2 1 123 4 v in (v) v out (v) 0 t a = 25 c v dd = 2.7v v dd = 2.5v v dd = 2.3v figure a1-46 input characteristics (cmos) ? schmitt-trigger type input buffers 4 3 2 1 123 4 v in (v) v out (v) 0 t a = 25 c v dd = 2.7v v dd = 2.5v v dd = 2.3v figure a1-47 input characteristics (cmos schmitt) appendix a1 electrical characteristics data (x type) embedded array S1X60000 series epson 291 design guide a1.2.2 input through current (2.5 v 0.2 v) 0 200u 400u 600u 800u 1m 1.2m 1.4m 1.6m 1.8m v dd = 2.7v voltage x (lin) (volts) currents (lin) 200m 400m 600m 800m 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 0 figure a1-48 input through current (cmos) 0 200u 300u 350u 250u 50u 100u 150u 400u 500u 600u 700u 450u 550u 650u v dd = 2.7v voltage x (lin) (volts) currents (lin) 200m 400m 600m 800m 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 0 figure a1-49 input through current (cmos schmitt) appendix a1 electrical characteristics data (x type) 292 epson embedded array S1X60000 series design guide a1.2.3 output buffer characteristics (2.5 v 0.2 v) (1) list of output buffer specifications table a1-2 output current characteristics output current type number i oh *1 i ol *2 unit type s -0.1 0.1 ma type m -1 1 ma type 1 -3 3 ma type 2 -6 6 ma type 3 -9 9 ma note *1: v oh = v dd - 0.4 v (v dd = 2.5 v) *2: v ol = 0.4 v (v dd = 2.5 v) appendix a1 electrical characteristics data (x type) embedded array S1X60000 series epson 293 design guide (2) i ol -v ol and i oh -v oh z i ol -v ol i ol (ma) 1.0 0.5 t a = 25 c 1.0 v ol (v) type s 0.5 0.0 0 v dd = 2.7v v dd = 2.5v v dd = 2.3v figure a1-50 i ol (ma) 10 5 t a = 25 c 1.0 v ol (v) type m 0.5 0.0 0 v dd = 2.7v v dd = 2.5v v dd = 2.3v figure a1-51 i ol (ma) 20 10 t a = 25 c 1.0 v ol (v) type 1 0.5 0.0 0 v dd = 2.7v v dd = 2.5v v dd = 2.3v figure a1-52 i ol (ma) 50 25 t a = 25 c 1.0 v ol (v) type 2 0.5 0.0 0 v dd = 2.7v v dd = 2.5v v dd = 2.3v figure a1-53 i ol (ma) 100 50 t a = 25 c 1.0 v ol (v) type 3 0.5 0.0 0 v dd = 2.7v v dd = 2.5v v dd = 2.3v figure a1-54 i ol (ma) 100 50 t a = 25 c 1.0 v ol (v) type 1 to 3 0.5 0.0 0 v dd = 2.5v type 3 type 2 type 1 figure a1-55 appendix a1 electrical characteristics data (x type) 294 epson embedded array S1X60000 series design guide z i oh -v oh i oh (ma) -1.0 -0.5 0.0 t a = 25 c -1.0 type s -0.5 v dd = 2.7v v dd = 2.5v v dd = 2.3v output voltage v oh - supply voltage v dd (v) figure a1-56 i oh (ma) -10 -5 0.0 t a = 25 c -1.0 type m -0.5 v dd = 2.7v v dd = 2.5v v dd = 2.3v output voltage v oh - supply voltage v dd (v) figure a1-57 i oh (ma) -20 -10 0 t a = 25 c -1.0 type 1 -0.5 0.0 v dd = 2.7v v dd = 2.5v v dd = 2.3v output voltage v oh - supply voltage v dd (v) figure a1-58 i oh (ma) -50 -25 0 t a = 25 c -1.0 type 2 -0.5 0.0 v dd = 2.7v v dd = 2.5v v dd = 2.3v output voltage v oh - supply voltage v dd (v) figure a1-59 i oh (ma) -100 -50 0 t a = 25 c -1.0 type 3 -0.5 0.0 v dd = 2.7v v dd = 2.5v v dd = 2.3v output voltage v oh - supply voltage v dd (v) figure a1-60 i oh (ma) -100 -50 0 t a = 25 c -1.0 type 1 to 3 -0.5 0.0 v dd = 2.5v type 3 type 2 type 1 output voltage v oh - supply voltage v dd (v) figure a1-61 appendix a1 electrical characteristics data (x type) embedded array S1X60000 series epson 295 design guide (3) i ol and i oh temperature characteristics 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 i ol (ratio) -40 -20 -60 20 040 t a ( c) 60 80 100 120 140 v dd = 2.5v i ol = 1.0 (t a = 25 c) figure a1-62 ambient temperature (t a ) - output current (i ol ) 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 i oh (ratio) -40 -20 -60 20 040 t a ( c) 60 80 100 120 140 v dd = 2.5v i oh = 1.0 (t a = 25 c) figure a1-63 ambient temperature (t a ) - output current (i oh ) (4) output delay time vs. output load capacitance (c l ) 0 100 200 300 400 0 50 100 50 200 c l (pf) t plh (ns) v dd = 2.5v v l = 1.25v t a = 25 c xobmt xobst figure a1-64 output delay time (t plh ) vs. output load capacitance (c l ) 0 100 200 300 400 0 50 100 150 200 c l (pf) t phl (ns) v dd = 2.5v v l = 1.25v t a = 25 c xobmt xobst figure a1-65 output delay time (t phl ) vs. output load capacitance (c l ) 0 5 10 15 20 0 50 100 150 200 c l (pf) t plh (ns) v dd = 2.5v v l = 1.25v t a = 25 c xob2t xob3t xob1t figure a1-66 output delay time (t plh ) vs. output load capacitance (c l ) 0 5 10 15 20 0 50 100 150 200 c l (pf) t phl (ns) v dd = 2.5v v l = 1.25v t a = 25 c xob2t xob3t xob1t figure a1-67 output delay time (t phl ) vs. output load capacitance (c l ) appendix a1 electrical characteristics data (x type) 296 epson embedded array S1X60000 series design guide (5) output buffer rising/falling time vs. output load capacitance (c l ) 0 200 400 600 800 0 50 100 150 200 c l (pf) t r (0%-90%) (ns) v dd = 2.5v v l = 1.25v t a = 25 c xobmt xobst figure a1-68 rising time (t r ) vs. output load capacitance (c l ) 0 200 400 600 800 0 50 100 150 200 c l (pf) t f (0%-90%) (ns) v dd = 2.5v v l = 1.25v t a = 25 c xobmt xobst figure a1-69 falling time (t f ) vs. output load capacitance (c l ) 0 10 20 30 40 0 50 100 150 200 c l (pf) t r (0%-90%) (ns) v dd = 2.5v v l = 1.25v t a = 25 c xob2t xob3t xob1t figure a1-70 rising time (t r ) vs. output load capacitance (c l ) 0 10 20 30 40 0 50 100 150 200 c l (pf) t f (0%-90%) (ns) v dd = 2.5v v l = 1.25v t a = 25 c xob2t xob3t xob1t figure a1-71 falling time (t f ) vs. output load capacitance (c l ) appendix a1 electrical characteristics data (x type) embedded array S1X60000 series epson 297 design guide (6) pull-up and pull-down resistance z pull-up characteristics 2.1 v dd (v) r plu (k ? ) 2.3 2.5 2.7 2.9 t a = 25 c type 1 type 2 250 200 150 100 50 0 figure a1-72 pull-up resistance (r plu ) vs. v dd -60 -40 -20 0 20 40 60 80 100 120 140 t a ( c) r plu (k ? ) type 1 type 2 200 150 100 50 0 v dd = 2.5v figure a1-73 pull-up resistance (r plu ) vs. ambient temperature z pull-down characteristics 2.1 v dd (v) r pld (k ? ) 2.3 2.5 2.7 2.9 t a = 25 c type 1 type 2 250 200 150 100 50 0 figure a1-74 pull-down resistance (r pld ) vs. v dd -60 -40 -20 0 20 40 60 80 100 120 140 t a ( c) r pld (k ? ) type 1 type 2 200 150 100 50 0 v dd = 2.5v figure a1-75 pull-down resistance (r pld ) vs. ambient temperature (t a ) appendix a1 electrical characteristics data (x type) 298 epson embedded array S1X60000 series design guide (7) output waveforms z high speed type output buffer conditions: v dd = 2.5v, t a = 25 c, c l = 15pf, i ol = 9 ma 4 3 2 1 0 -1 output voltage v o (v) (5 ns/div) figure a1-76 output waveform (xob3at) z normal type output buffer conditions: v dd = 2.5v, t a = 25 c, c l = 15pf, i ol = 9 ma 4 3 2 1 0 -1 output voltage v o (v) (5 ns/div) figure a1-77 output waveform (xob3t) z low noise type output buffer conditions: v dd = 2.5v, t a = 25 c, c l = 15pf, i ol = 9 ma 4 3 2 1 0 -1 output voltage v o (v) (5 ns/div) figure a1-78 output waveform (xob3bt) appendix a1 electrical characteristics data (x type) embedded array S1X60000 series epson 299 design guide a1.3 characteristics of input/output buffers (2.0 v operation) a1.3.1 input buffer characteristics (2.0 v 0.2 v) ? standard type input buffers 3 2 1 123 v in (v) v out (v) 0 t a = 25 c v dd = 2.2v v dd = 2.0v v dd = 1.8v figure a1-79 input characteristics (cmos) ? schmitt-trigger type input buffers 3 2 1 123 v in (v) v out (v) 0 t a = 25 c v dd = 2.2v v dd = 2.0v v dd = 1.8v figure a1-80 input characteristics (cmos schmitt) appendix a1 electrical characteristics data (x type) 300 epson embedded array S1X60000 series design guide a1.3.2 input through current (2.0 v 0.2 v) 0 200u 400u 600u 800u 1m v dd = 2.2v voltage x (lin) (volts) currents (lin) 200m 400m 600m 800m 1 1.2 1.4 1.6 1.8 2 2.2 0 figure a1-81 input through current (cmos) 0 200u 100u 250u 150u 50u 400u 350u 300u v dd = 2.2v voltage x (lin) (volts) currents (lin) 200m 400m 600m 800m 1 1.2 1.4 1.6 1.8 2 2.2 0 figure a1-82 input through current (cmos schmitt) appendix a1 electrical characteristics data (x type) embedded array S1X60000 series epson 301 design guide a1.3.3 output buffer characteristics (2.0 v 0.2 v) (1) list of output buffer specifications table a1-3 output current characteristics output current type number i oh *1 i ol *2 unit type s -0.05 0.05 ma type m -0.3 0.3 ma type 1 -1 1 ma type 2 -2 2 ma type 3 -3 3 ma note *1: v oh = v dd - 0.2 v (v dd = 2.0 v) *2: v ol = 0.2 v (v dd = 2.0 v) appendix a1 electrical characteristics data (x type) 302 epson embedded array S1X60000 series design guide (2) i oh -v ol and i oh -v oh z i ol -v ol i ol (ma) 1.0 0.5 t a = 25 c 1.0 v ol (v) type s 0.5 0.0 0 v dd = 2.2v v dd = 2.0v v dd = 1.8v figure a1-83 i ol (ma) 10 5 t a = 25 c 1.0 v ol (v) type m 0.5 0.0 0 v dd = 2.2v v dd = 2.0v v dd = 1.8v figure a1-84 i ol (ma) 20 10 t a = 25 c 1.0 v ol (v) type 1 0.5 0.0 0 v dd = 2.2v v dd = 2.0v v dd = 1.8v figure a1-85 i ol (ma) 50 25 t a = 25 c 1.0 v ol (v) type 2 0.5 0.0 0 v dd = 2.2v v dd = 2.0v v dd = 1.8v figure a1-86 i ol (ma) 100 50 t a = 25 c 1.0 v ol (v) type 3 0.5 0.0 0 v dd = 2.2v v dd = 2.0v v dd = 1.8v figure a1-87 i ol (ma) 100 50 t a = 25 c 1.0 v ol (v) type 1 to 3 0.5 0.0 0 hv dd = 2.0v type 3 type 2 type 1 figure a1-88 appendix a1 electrical characteristics data (x type) embedded array S1X60000 series epson 303 design guide z i oh -v oh i oh (ma) -1.0 -0.5 0.0 t a = 25 c -1.0 type s -0.5 v dd = 2.2v v dd = 2.0v v dd = 1.8v output voltage v oh - supply voltage v dd (v) figure a1-89 i oh (ma) -10 -5 0.0 t a = 25 c -1.0 type m -0.5 v dd = 2.2v v dd = 2.0v v dd = 1.8v output voltage v oh - supply voltage v dd (v) figure a1-90 i oh (ma) -20 -10 0 t a = 25 c -1.0 type 1 -0.5 0.0 v dd = 2.2v v dd = 2.0v v dd = 1.8v output voltage v oh - supply voltage v dd (v) figure a1-91 i oh (ma) -50 -25 0 t a = 25 c -1.0 type 2 -0.5 0.0 v dd = 2.2v v dd = 2.0v v dd = 1.8v output voltage v oh - supply voltage v dd (v) figure a1-92 i oh (ma) -100 -50 0 t a = 25 c -1.0 type 3 -0.5 0.0 v dd = 2.2v v dd = 2.0v v dd = 1.8v output voltage v oh - supply voltage v dd (v) figure a1-93 i oh (ma) -100 -50 0 t a = 25 c -1.0 type 1 to 3 -0.5 0.0 v dd = 2.0v type 3 type 2 type 1 output voltage v oh - supply voltage v dd (v) figure a1-94 appendix a1 electrical characteristics data (x type) 304 epson embedded array S1X60000 series design guide (3) i ol and i oh temperature characteristics 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 i ol (ratio) -40 -20 -60 20 040 t a ( c) 60 80 100 120 140 v dd = 2.0v i ol = 1.0 (t a = 25 c) figure a1-95 ambient temperature (t a ) - output current (i ol ) 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 i oh (ratio) -40 -20 -60 20 040 t a ( c) 60 80 100 120 140 v dd = 2.0v i oh = 1.0 (t a = 25 c) figure a1-96 ambient temperature (t a ) - output current (i oh ) (4) output delay time vs. output load capacitance (c l ) 0 100 200 300 400 0 50 100 150 200 c l (pf) t phl (ns) v dd = 2.0v v l = 1.0v t a = 25 c xobmt xobst figure a1-97 output delay time (t plh ) vs. output load capacitance (c l ) 0 100 200 300 400 0 50 100 150 200 c l (pf) t phl (ns) v dd = 2.0v v l = 1.0v t a = 25 c xobmt xobst figure a1-98 output delay time (t phl ) vs. output load capacitance (c l ) 0 5 10 15 20 0 50 100 150 200 c l (pf) t phl (ns) v dd = 2.0v v l = 1.0v t a = 25 c xob2t xob3t xob1t figure a1-99 output delay time (t plh ) vs. output load capacitance (c l ) 0 5 10 15 20 0 50 100 150 200 c l (pf) t phl (ns) v dd = 2.0v v l = 1.0v t a = 25 c xob2t xob3t xob1t figure a1-100 output delay time (t phl ) vs. output load capacitance (c l ) appendix a1 electrical characteristics data (x type) embedded array S1X60000 series epson 305 design guide (5) output buffer rising/falling time vs. output load capacitance (c l ) 0 200 400 600 800 0 50 100 150 200 c l (pf) t r (0%-90%) (ns) v dd = 2.0v v l = 1.0v t a = 25 c xobmt xobst figure a1-101 rising time (t r ) vs. output load capacitance (c l ) 0 200 400 600 800 0 100 150 200 c l (pf) t f (0%-90%) (ns) v dd = 2.0v v l = 1.0v t a = 25 c xobmt xobst 50 figure a1-102 falling time (t f ) vs. output load capacitance (c l ) 0 0 20 30 40 0 50 100 150 200 c l (pf) t r (0%-90%) (ns) v dd = 2.0v v l = 1.0v t a = 25 c xob2t xob3t xob1t figure a1-103 rising time (t r ) vs. output load capacitance (c l ) 0 0 20 30 40 0 50 100 150 200 c l (pf) t f (0%-90%) (ns) v dd = 2.0v v l = 1.0v t a = 25 c xob2t xob3t xob1t figure a1-104 falling time (t f ) vs. output load capacitance (c l ) appendix a1 electrical characteristics data (x type) 306 epson embedded array S1X60000 series design guide (6) pull-up and pull-down resistance z pull-up characteristics 1.6 v dd (v) r plu (k ? ) 1.8 2.0 2.2 2.4 t a = 25 c type 1 type 2 250 200 150 100 50 0 figure a1-105 pull-up resistance (r plu ) vs. v dd -60 -40 -20 0 20 40 60 80 100 120 140 t a ( c) r plu (k ? ) type 1 type 2 200 150 100 50 0 v dd = 2.0v figure a1-106 pull-up resistance (r plu ) vs. ambient temperature z pull-down characteristics 1.6 v dd (v) r pld (k ? ) 1.8 2 2.2 2.4 t a = 25 c type 1 type 2 250 200 150 100 50 0 figure a1-107 pull-down resistance (r pld ) vs. v dd -60 -40 -20 0 20 40 60 80 100 120 140 t a ( c) r pld (k ? ) type 1 type 2 200 150 100 50 0 v dd = 2.0v figure a1-108 pull-down resistance (r pld ) vs. ambient temperature (t a ) appendix a1 electrical characteristics data (x type) embedded array S1X60000 series epson 307 design guide (7) output waveforms z high speed type output buffer conditions: v dd = 2.0v, t a = 25 c, c l = 15pf, i ol = 3 ma 3 2.5 2 1.5 1 0.5 0 -0.5 -1 output voltage v o (v) (5 ns/div) figure a1-109 output waveform (xob3at) z normal type output buffer conditions: v dd = 2.0v, t a = 25 c, c l = 15pf, i ol = 3 ma 3 2.5 2 1.5 1 0.5 0 -0.5 -1 output voltage v o (v) (5 ns/div) figure a1-110 output waveform (xob3t) z low noise type output buffer conditions: v dd = 2.0v, t a = 25 c, c l = 15pf, i ol = 3 ma 3 2.5 2 1.5 1 0.5 0 -0.5 -1 output voltage v o (v) (5 ns/div) figure a1-111 output waveform (xob3bt) appendix a2 electrical characteristics data (xf type) 308 epson embedded array S1X60000 series design guide appendix a2 electrical characteristics data (xf type) a2.1 characteristics of input/output buffers (3.3 v operation) a2.1.1 input buffer characteristics (3.3 v 0.3 v) ? standard type input buffers 4 3 2 1 123 4 v in (v) v out (v) 0 t a = 25 c hv dd = 3.6v hv dd = 3.3v hv dd = 3.0v figure a2-1 input characteristics (lvttl) 4 3 2 1 123 4 v in (v) v out (v) 0 t a = 25 c hv dd = 3.6v hv dd = 3.3v hv dd = 3.0v figure a2-2 input characteristics (cmos) 4 3 2 1 123 4 v in (v) v out (v) 0 t a = 25 c hv dd = 3.6v hv dd = 3.3v hv dd = 3.0v figure a2-3 input characteristics (pci-3v) ? schmitt-trigger type input buffers 4 3 2 1 123 4 v in (v) v out (v) 0 t a = 25 c hv dd = 3.6v hv dd = 3.3v hv dd = 3.0v figure a2-4 input characteristics (lvttl schmitt) 4 3 2 1 123 4 v in (v) v out (v) 0 t a = 25 c hv dd = 3.6v hv dd = 3.3v hv dd = 3.0v figure a2-5 input characteristics (cmos schmitt) appendix a2 electrical characteristics data (xf type) embedded array S1X60000 series epson 309 design guide a2.1.2 input through current (3.3 v 0.3 v) 0 0 200u 400u 600u 800u 1m 1.2m 1.4m 1.6m 1.8m 2m 2.2m 2.4m 2.6m hv dd /lv dd = 3.6v/2.7v 11.5 voltage x (lin) (volts) currents (lin) 33.5 2.5 2 500m figure a2-6 input through current (cmos) 0 0 200u 400u 600u 800u 1m hv dd /lv dd = 3.6v/2.7v 11.5 voltage x (lin) (volts) currents (lin) 33.5 2.5 2 500m figure a2-7 input through current (cmos schmitt) appendix a2 electrical characteristics data (xf type) 310 epson embedded array S1X60000 series design guide 0 0 200u 400u 600u 800u 1m 1.2m 1.4m 1.6m 1.8m 2m 2.2m 2.4m 2.6m 2.8m hv dd /lv dd = 3.6v/2.7v 1 1.5 voltage x (lin) (volts) currents (lin) 3 3.5 2.5 2 500m figure a2-8 input through current (lvttl) 0 0 200u 400u 600u 800u 1m 1.2m hv dd /lv dd = 3.6v/2.7v 1 1.5 voltage x (lin) (volts) currents (lin) 33.5 2.5 2 500m figure a2-9 input through current (lvttl schmitt) appendix a2 electrical characteristics data (xf type) embedded array S1X60000 series epson 311 design guide 0 0 200u 400u 600u 800u 1m 1.2m 1.4m 1.6m 1.8m 2m 2.2m 2.4m 2.6m 2.8m 3m hv dd /lv dd = 3.6v/2.7v 11.5 voltage x (lin) (volts) currents (lin) 33.5 2.5 2 500m figure a2-10 input through current (pci) appendix a2 electrical characteristics data (xf type) 312 epson embedded array S1X60000 series design guide a2.1.3 output buffer characteristics (3.3 v 0.3 v) (1) list of output buffer specifications table a2-1 output current characteristics output current type number i oh *1 i ol *2 unit type s -0.1 0.1 ma type m -1 1 ma type 1 -3 3 ma type 2 -6 6 ma type 3 -12 12 ma pci confirmed to the pci standard ma note *1: v oh = hv dd - 0.4 v (hv dd = 3.3v) *2: v ol = 0.4 v (hv dd = 3.3 v) appendix a2 electrical characteristics data (xf type) embedded array S1X60000 series epson 313 design guide (2) i ol -v ol and i oh -v oh z i oh -v ol 1.0 0.5 t a = 25 c 1.0 i ol (ma) v ol (v) type s 0.5 0.0 0 hv dd = 3.6v hv dd = 3.3v hv dd = 3.0v figure a2-11 10 5 t a = 25 c 1.0 i ol (ma) v ol (v) type m 0.5 0.0 0 hv dd = 3.6v hv dd = 3.3v hv dd = 3.0v figure a2-12 20 10 t a = 25 c 1.0 i ol (ma) v ol (v) type 1 0.5 0.0 0 hv dd = 3.6v hv dd = 3.3v hv dd = 3.0v figure a2-13 50 25 t a = 25 c 1.0 i ol (ma) v ol (v) type 2 0.5 0.0 0 hv dd = 3.6v hv dd = 3.3v hv dd = 3.0v figure a2-14 100 50 t a = 25 c 1.0 i ol (ma) v ol (v) type 3 0.5 0.0 0 hv dd = 3.6v hv dd = 3.3v hv dd = 3.0v figure a2-15 100 50 t a = 25 c 1.0 i ol (ma) v ol (v) pci 3v 0.5 0.0 0 hv dd = 3.6v hv dd = 3.3v hv dd = 3.0v figure a2-16 appendix a2 electrical characteristics data (xf type) 314 epson embedded array S1X60000 series design guide 100 50 t a = 25 c 1.0 i ol (ma) v ol (v) type 1 to 3 0.5 0.0 0 hv dd = 3.3v type 3 ty p e 2 type 1 figure a2-17 z i oh -v oh i oh (ma) -1.0 -0.5 0.0 t a = 25 c -1.0 type s -0.5 hv dd = 3.6v hv dd = 3.3v hv dd = 3.0v output voltage v oh - suplly voltage hv dd (v) figure a2-18 i oh (ma) -1.0 -0.5 0.0 t a = 25 c -1.0 type m -0.5 hv dd = 3.6v hv dd = 3.3v hv dd = 3.0v output voltage v oh - suplly voltage hv dd (v) figure a2-19 i oh (ma) -20 -10 0 t a = 25 c -1.0 type 1 -0.5 0.0 hv dd = 3.6v hv dd = 3.3v hv dd = 3.0v output voltage v oh - suplly voltage hv dd (v) figure a2-20 i oh (ma) -50 -25 0 t a = 25 c -1.0 type 2 -0.5 0.0 hv dd = 3.6v hv dd = 3.3v hv dd = 3.0v output voltage v oh - suplly voltage hv dd (v) figure a2-21 appendix a2 electrical characteristics data (xf type) embedded array S1X60000 series epson 315 design guide i oh (ma) -100 -50 0 t a = 25 c -1.0 type 3 -0.5 0.0 hv dd = 3.6v hv dd = 3.3v hv dd = 3.0v output voltage v oh - suplly voltage hv dd (v) figure a2-22 i oh (ma) -100 -50 0 t a = 25 c -1.0 pci 3v -0.5 0.0 hv dd = 3.6v hv dd = 3.3v hv dd = 3.0v output voltage v oh - suplly voltage hv dd (v) figure a2-23 i oh (ma) -100 -50 0 t a = 25 c -1.0 type 1 to 3 -0.5 0.0 hv dd = 3.3v type 3 type 2 type 1 output voltage v oh - suplly voltage hv dd (v) figure a2-24 (3) i ol and i oh temperature characteristics 1.40 1.30 1.20 1.10 1.00 0.90 0.80 0.70 0.60 i ol (ratio) -40 -20 -60 20 040 t a ( c) 60 80 100 120 140 hv dd = 3.3v i ol = 1.0 (t a = 25 c) figure a2-25 ambient temperature (t a ) - output current (i ol ) 1.40 1.30 1.20 1.10 1.00 0.90 0.80 0.70 0.60 i oh (ratio) -40 -20 -60 20 040 t a ( c) 60 80 100 120 140 hv dd = 3.3v i oh = 1.0 (t a = 25 c) figure a2-26 ambient temperature (t a ) - output current (i oh ) appendix a2 electrical characteristics data (xf type) 316 epson embedded array S1X60000 series design guide (4) output delay time vs. output load capacitance (c l ) 0 00 200 300 400 0 50 100 150 200 c l (pf) t plh (ns) hv dd = 3.3v v l = 1.65v t a = 25 c xfhobmt xfhobst figure a2-27 output delay time (t plh ) vs. output load capacitance (c l ) 0 00 200 300 400 0 50 100 150 200 c l (pf) t phl (ns) hv dd = 3.3v v l = 1.65v t a = 25 c xfhobmt xfhobst figure a2-28 output delay time (t phl ) vs. output load capacitance (c l ) 0 5 0 5 20 0 50 100 150 200 c l (pf) t plh (ns) hv dd = 3.3v v l = 1.65v t a = 25 c xfhob2t xfhob3t xfhobt figure a2-29 output delay time (t plh ) vs. output load capacitance (c l ) 0 5 0 5 20 0 50 100 150 200 c l (pf) t phl (ns) hv dd = 3.3v v l = 1.65v t a = 25 c xfhob2t xfhob3t xfhob1t figure a2-30 output delay time (t phl ) vs. output load capacitance (c l ) 0 2 3 4 5 0 50 100 150 200 c l (pf) t plh (ns) hv dd = 3.3v v l = 1.65v t a = 25 c xfhobpb figure a2-31 output delay time (t plh ) vs. output load capacitance (c l ) 0 2 3 4 5 0 50 100 150 200 c l (pf) t phl (ns) hv dd = 3.3v v l = 1.65v t a = 25 c xfhobpbt figure a2-32 output delay time (t phl ) vs. output load capacitance (c l ) appendix a2 electrical characteristics data (xf type) embedded array S1X60000 series epson 317 design guide (5) output buffer rising/falling time vs. output load capacitance (c l ) 0 200 400 600 800 0 50 100 50 200 c l (pf) t r (0%-90%) (ns) hv dd = 3.3v v l = 1.65v t a = 25 c xfhobmt xfhobst figure a2-33 rising time (t r ) vs. output load capacitance (c l ) 0 200 400 600 800 c l (pf) t f (0%-90%) (ns) hv dd = 3.3v v l = 1.65v t a = 25 c 0 50 100 50 200 xfhobmt xfhobst figure a2-34 falling time (t f ) vs. output load capacitance (c l ) 0 0 20 30 40 c l (pf) t r (0%-90%) (ns) hv dd = 3.3v v l = 1.65v t a = 25 c xfhob2t xfhob3t xfhob1t 0 50 100 50 200 figure a2-35 rising time (t r ) vs. output load capacitance (c l ) 0 0 20 30 40 c l (pf) t f (0%-90%) (ns) hv dd = 3.3v v l = 1.65v t a = 25 c xfhob2t xfhob3t xfhob1t 0 50 100 50 200 figure a2-36 falling time (t f ) vs. output load capacitance (c l ) 0 2 4 6 8 0 c l (pf) t r (0%-90%) (ns) 0 50 100 50 200 hv dd = 3.3v v l = 1.65v t a = 25 c xfhobpbt figure a2-37 rising time (t r ) vs. output load capacitance (c l ) 0 2 4 6 8 0 c l (pf) t f (0%-90%) (ns) hv dd = 3.3v v l = 1.65v t a = 25 c 0 50 100 150 200 xfhobpbt figure a2-38 falling time (t f ) vs. output load capacitance (c l ) appendix a2 electrical characteristics data (xf type) 318 epson embedded array S1X60000 series design guide (6) pull-up and pull-down resistnace z pull-up characteristics 2.4 hv dd (v) r plu (k ? ) 2.7 3 3.3 3.6 3.9 4.2 t a = 25 c type 1 type 2 250 200 150 100 50 0 figure a2-39 pull-up resistance (r plu ) vs. hv dd -60 -40 -20 0 20 40 60 80 100 120 140 t a ( c) r plu (k ? ) type 1 type 2 250 200 150 100 50 0 hv dd = 3.3v figure a2-40 pull-up resistance (r plu ) vs. ambient temperature z pull-down characteristics 2.4 hv dd (v) r pld (k ? ) 2.7 3 3.3 3.6 3.9 4.2 t a = 25 c type 1 type 2 250 200 150 100 50 0 figure a2-41 pull-down resistance (r pld ) vs. hv dd -60 -40 -20 0 20 40 60 80 100 120 140 t a ( c) r pld (k ? ) type 1 type 2 250 200 150 100 50 0 hv dd = 3.3v figure a2-42 pull-down resistance (r pld ) vs. ambient temperature appendix a2 electrical characteristics data (xf type) embedded array S1X60000 series epson 319 design guide (7) output waveforms z high speed type output buffer conditions: hv dd = 3.3v, t a = 25 c, c l = 15pf, i ol = 12 ma 6 4 2 0 -2 output voltage v o (v) (5 ns/div) figure a2-43 output waveform (xfhob3at) z normal type output buffer conditions: hv dd = 3.3v, t a = 25 c, c l = 15pf, i ol = 12 ma 6 4 2 0 -2 output voltage v o (v) (5 ns/div) figure a2-44 output waveform (xfhob3t) z low noise type output buffer conditions: hv dd = 3.3v, t a = 25 c, c l = 15pf, i ol = 12 ma 6 4 2 0 -2 output voltage v o (v) (5 ns/div) figure a2-45 output waveform (xfhob3bt) appendix a2 electrical characteristics data (xf type) 320 epson embedded array S1X60000 series design guide a2.2 characteristics of input/output buffers (2.5 v operation) a2.2.1 input buffer characteristics (2.5 v 0.2 v) ? standard type input buffers 4 3 2 1 123 4 v in (v) v out (v) 0 t a = 25 c lv dd = 2.7v lv dd = 2.5v lv dd = 2.3v figure a2-46 input characteristics (cmos) ? schmitt-trigger type input buffers 4 3 2 1 123 4 v in (v) v out (v) 0 t a = 25 c lv dd = 2.7v lv dd = 2.5v lv dd = 2.3v figure a2-47 input characteristics (cmos schmitt) appendix a2 electrical characteristics data (xf type) embedded array S1X60000 series epson 321 design guide a2.2.2 input through current (2.5 v 0.2 v) 0 200u 400u 600u 800u 1m 1.2m 1.4m 1.6m 1.8m v dd = 2.7v voltage x (lin) (volts) currents (lin) 200m 400m 600m 800m 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 0 figure a2-48 input through current (cmos) 0 200u 300u 350u 250u 50u 100u 150u 400u 500u 600u 700u 450u 550u 650u v dd = 2.7v voltage x (lin) (volts) currents (lin) 200m 400m 600m 800m 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 0 figure a2-49 input through current (cmos schmitt) appendix a2 electrical characteristics data (xf type) 322 epson embedded array S1X60000 series design guide a2.2.3 output buffer characteristics (2.5 v 0.2 v) (1) list of output buffer specifications table a2-2 output current characteristics output current type number i oh *1 i ol *2 unit type s -0.1 0.1 ma type m -1 1 ma type 1 -3 3 ma type 2 -6 6 ma type 3 -9 9 ma note *1: v oh = v dd - 0.4 v (v dd = 2.5 v) *2: v ol = 0.4 v (v dd = 2.5 v) appendix a2 electrical characteristics data (xf type) embedded array S1X60000 series epson 323 design guide (2) i ol -v ol and i oh -v oh z i ol -v ol i ol (ma) 1.0 0.5 t a = 25 c 1.0 v ol (v) type s 0.5 0.0 0 lv dd = 2.7v lv dd = 2.5v lv dd = 2.3v figure a2-50 i ol (ma) 10 5 t a = 25 c 1.0 v ol (v) type m 0.5 0.0 0 lv dd = 2.7v lv dd = 2.5v lv dd = 2.3v figure a2-51 i ol (ma) 20 10 t a = 25 c 1.0 v ol (v) type 1 0.5 0.0 0 lv dd = 2.7v lv dd = 2.5v lv dd = 2.3v figure a2-52 i ol (ma) 50 25 t a = 25 c 1.0 v ol (v) type 2 0.5 0.0 0 lv dd = 2.7v lv dd = 2.5v lv dd = 2.3v figure a2-53 i ol (ma) 100 50 t a = 25 c 1.0 v ol (v) type 3 0.5 0.0 0 lv dd = 2.7v lv dd = 2.5v lv dd = 2.3v figure a2-54 i ol (ma) 100 50 t a = 25 c 1.0 v ol (v) type 1 to 3 0.5 0.0 0 lv dd = 2.5v type 3 type 2 type 1 figure a2-55 appendix a2 electrical characteristics data (xf type) 324 epson embedded array S1X60000 series design guide z i oh -v oh i oh (ma) -1.0 -0.5 0.0 t a = 25 c -1.0 type s -0.5 lv dd = 2.7v lv dd = 2.5v lv dd = 2.3v output voltage v oh - supply voltage lv dd (v) figure a2-56 i oh (ma) -10 -5 0.0 t a = 25 c -1.0 type m -0.5 lv dd = 2.7v lv dd = 2.5v lv dd = 2.3v output voltage v oh - supply voltage lv dd (v) figure a2-57 i oh (ma) -20 -10 0 t a = 25 c -1.0 type 1 -0.5 0.0 lv dd = 2.7v lv dd = 2.5v lv dd = 2.3v output voltage v oh - supply voltage lv dd (v) figure a2-58 i oh (ma) -50 -25 0 t a = 25 c -1.0 type 2 -0.5 0.0 lv dd = 2.7v lv dd = 2.5v lv dd = 2.3v output voltage v oh - supply voltage lv dd (v) figure a2-59 i oh (ma) -100 -50 0 t a = 25 c -1.0 type 3 -0.5 0.0 lv dd = 2.7v lv dd = 2.5v lv dd = 2.3v output voltage v oh - supply voltage lv dd (v) figure a2-60 i oh (ma) -100 -50 0 t a = 25 c -1.0 type 1 to 3 -0.5 0.0 lv dd = 2.5v type 3 type 2 type 1 output voltage v oh - supply voltage lv dd (v) a2-61 appendix a2 electrical characteristics data (xf type) embedded array S1X60000 series epson 325 design guide (3) i ol and i oh temperature characteristics 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 i ol (ratio) -40 -20 -60 20 040 t a ( c) 60 80 100 120 140 lv dd = 2.5v i ol = 1.0 (t a = 25 c) figure a2-62 ambient temperature (t a ) - output current (i ol ) 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 i oh (ratio) -40 -20 -60 20 040 t a ( c) 60 80 100 120 140 lv dd = 2.5v i oh = 1.0 (t a = 25 c) figure a2-63 ambient temperature (t a ) - output current (i oh ) (4) output delay time vs. output load capacitance (c l ) 0 100 200 300 400 0 50 100 50 200 c l (pf) t plh (ns) lv dd = 2.5v v l = 1.25v t a = 25 c xflobmt xflobst figure a2-64 output delay time (t plh ) vs. output load capacitance (c l ) 0 100 200 300 400 0 50 100 150 200 c l (pf) t phl (ns) lv dd = 2.5v v l = 1.25v t a = 25 c xflobmt xflobst figure a2-65 output delay time (t phl ) vs. output load capacitance (c l ) 0 5 10 15 20 0 50 100 150 200 c l (pf) t plh (ns) lv dd = 2.5v v l = 1.25v t a = 25 c xflob2t xflob3t xflob1t figure a2-66 output delay time (t plh ) vs. output load capacitance (c l ) 0 5 10 15 20 0 50 100 150 200 c l (pf) t phl (ns) lv dd = 2.5v v l = 1.25v t a = 25 c xflob2t xflob3t xflob1t figure a2-67 output delay time (t phl ) vs. output load capacitance (c l ) appendix a2 electrical characteristics data (xf type) 326 epson embedded array S1X60000 series design guide (5) output buffer rising/falling time vs. output load capacitance (c l ) 0 200 400 600 800 0 50 100 150 200 c l (pf) t r (0%-90%) (ns) lv dd = 2.5v v l = 1.25v t a = 25 c xflobmt xflobst figure a2-68 rising time (t r ) vs. output load capacitance (c l ) 0 200 400 600 800 0 50 100 150 200 c l (pf) t f (0%-90%) (ns) lv dd = 2.5v v l = 1.25v t a = 25 c xflobmt xflobst figure a2-69 falling time (t f ) vs. output load capacitance (c l ) 0 10 20 30 40 0 50 100 150 200 c l (pf) t r (0%-90%) (ns) lv dd = 2.5v v l = 1.25v t a = 25 c xflob2t xflob3t xflob1t figure a2-70 rising time (t r ) vs. output load capacitance (c l ) 0 10 20 30 40 0 50 100 150 200 c l (pf) t f (0%-90%) (ns) lv dd = 2.5v v l = 1.25v t a = 25 c xflob2t xflob3t xflob1t figure a2-71 falling time (t f ) vs. output load capacitance (c l ) appendix a2 electrical characteristics data (xf type) embedded array S1X60000 series epson 327 design guide (6) pull-up and pull-down resistance z pull-up characteristics 2.1 lv dd (v) r plu (k ? ) 2.3 2.5 2.7 2.9 t a = 25 c type 1 type 2 250 200 150 100 50 0 figure a2-72 pull-up resistance (r plu ) vs. lv dd -60 -40 -20 0 20 40 60 80 100 120 140 t a ( c) r plu (k ? ) type 1 type 2 200 150 100 50 0 lv dd = 2.5v figure a2-73 pull-up resistance (r plu ) vs. ambient temperature (t a ) z pull-down characteristics 2.1 lv dd (v) r pld (k ? ) 2.3 2.5 2.7 2.9 t a = 25 c type 1 type 2 250 200 150 100 50 0 figure a2-74 pull-down resistance (r pld ) vs. lv dd -60 -40 -20 0 20 40 60 80 100 120 140 t a ( c) r pld (k ? ) type 1 type 2 200 150 100 50 0 lv dd = 2.5v figure a2-75 pull-down resistance (r pld ) vs. ambient temperature (t a ) appendix a2 electrical characteristics data (xf type) 328 epson embedded array S1X60000 series design guide (7) output wavefors z high speed type output buffer conditions: lv dd = 2.5v, t a = 25 c, c l = 15pf, i ol = 9 ma 4 3 2 1 0 -1 output voltage v o (v) (5 ns/div) figure a2-76 output waveform (xflob3at) z normal type output buffer conditions: lv dd = 2.5v, t a = 25 c, c l = 15pf, i ol = 9 ma 4 3 2 1 0 -1 output voltage v o (v) (5 ns/div) figure a2-77 output waveform (xflob3t) z low noise type output buffer conditions: lv dd = 2.5v, t a = 25 c, c l = 15pf, i ol = 9 ma 4 3 2 1 0 -1 output voltage v o (v) (5 ns/div) figure a2-78 output waveform (xflob3bt) appendix a2 electrical characteristics data (xf type) embedded array S1X60000 series epson 329 design guide a2.3 characteristics of input/output buffers (2.0 v operation) a2.3.1 input buffer characteristics (2.0 v 0.2 v) ? standard type input buffers 3 2 1 123 v in (v) v out (v) 0 t a = 25 c lv dd = 2.2v lv dd = 2.0v lv dd = 1.8v figure a2-79 input characteristics (cmos) ? schmitt-trigger type input buffers 3 2 1 123 v in (v) v out (v) 0 t a = 25 c lv dd = 2.2v lv dd = 2.0v lv dd = 1.8v figure a2-80 input characteristics (cmos schmitt) appendix a2 electrical characteristics data (xf type) 330 epson embedded array S1X60000 series design guide a2.3.2 input through current (2.0 v 0.2 v) 0 200u 400u 600u 800u 1m v dd = 2.2v voltage x (lin) (volts) currents (lin) 200m 400m 600m 800m 1 1.2 1.4 1.6 1.8 2 2.2 0 figure a2-81 input through current (cmos) 0 200u 100u 250u 150u 50u 400u 350u 300u v dd = 2.2v voltage x (lin) (volts) currents (lin) 200m 400m 600m 800m 1 1.2 1.4 1.6 1.8 2 2.2 0 figure a2-82 input through current (cmos schmitt) appendix a2 electrical characteristics data (xf type) embedded array S1X60000 series epson 331 design guide a2.3.3 output buffer characteristics (2.0 v 0.2 v) (1) list of output buffer specifications table a2-3 output current characteristics output current type number i oh *1 i ol *2 unit type s -0.05 0.05 ma type m -0.3 0.3 ma type 1 -1 1 ma type 2 -2 2 ma type 3 -3 3 ma note *1: v oh = v dd - 0.2 v (v dd = 2.0 v) *2: v ol = 0.2 v (v dd = 2.0 v) appendix a2 electrical characteristics data (xf type) 332 epson embedded array S1X60000 series design guide (2) i ol -v ol and i oh -v oh z i ol -v ol i ol (ma) 1.0 0.5 t a = 25 c 1.0 v ol (v) type s 0.5 0.0 0 lv dd = 2.2v lv dd = 2.0v lv dd = 1.8v figure a2-83 i ol (ma) 10 5 t a = 25 c 1.0 v ol (v) type m 0.5 0.0 0 lv dd = 2.2v lv dd = 2.0v lv dd = 1.8v figure a2-84 i ol (ma) 20 10 t a = 25 c 1.0 v ol (v) type 1 0.5 0.0 0 lv dd = 2.2v lv dd = 2.0v lv dd = 1.8v figure a2-85 i ol (ma) 50 25 t a = 25 c 1.0 v ol (v) type 2 0.5 0.0 0 lv dd = 2.2v lv dd = 2.0v lv dd = 1.8v figure a2-86 i ol (ma) 100 50 t a = 25 c 1.0 v ol (v) type 3 0.5 0.0 0 lv dd = 2.2v lv dd = 2.0v lv dd = 1.8v figure a2-87 i ol (ma) 100 50 t a = 25 c 1.0 v ol (v) type 1 to 3 0.5 0.0 0 lv dd = 2.0v type 3 type 2 type 1 figure a2-88 appendix a2 electrical characteristics data (xf type) embedded array S1X60000 series epson 333 design guide z i oh -v oh i oh (ma) -1.0 -0.5 0.0 t a = 25 c -1.0 type s -0.5 lv dd = 2.2v lv dd = 2.0v lv dd = 1.8v output voltage v oh - supply voltage lv dd (v) figure a2-89 i oh (ma) -10 -5 0.0 t a = 25 c -1.0 type m -0.5 lv dd = 2.2v lv dd = 2.0v lv dd = 1.8v output voltage v oh - supply voltage lv dd (v) figure a2-90 i oh (ma) -20 -10 0 t a = 25 c -1.0 type 1 -0.5 0.0 lv dd = 2.2v lv dd = 2.0v lv dd = 1.8v output voltage v oh - supply voltage lv dd (v) figure a2-91 i oh (ma) -50 -25 0 t a = 25 c -1.0 type 2 -0.5 0.0 lv dd = 2.2v lv dd = 2.0v lv dd = 1.8v output voltage v oh - supply voltage lv dd (v) figure a2-92 i oh (ma) -100 -50 0 t a = 25 c -1.0 type 3 -0.5 0.0 lv dd = 2.2v lv dd = 2.0v lv dd = 1.8v output voltage v oh - supply voltage lv dd (v) figure a2-93 i oh (ma) -100 -50 0 t a = 25 c -1.0 type 1 to 3 -0.5 0.0 lv dd = 2.0v type 3 type 2 type 1 output voltage v oh - supply voltage lv dd (v) figure a2-94 appendix a2 electrical characteristics data (xf type) 334 epson embedded array S1X60000 series design guide (3) i ol and i oh temperature characteristics 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 i ol (ratio) -40 -20 -60 20 040 t a ( c) 60 80 100 120 140 lv dd = 2.0v i ol = 1.0 (t a = 25 c) figure a2-95 ambient temperature (t a ) - output current (i ol ) 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 i oh (ratio) -40 -20 -60 20 040 t a ( c) 60 80 100 120 140 lv dd = 2.0v i oh = 1.0 (t a = 25 c) figure a2-96 ambient temperature (t a ) - output current (i oh ) (4) output delay time vs. output load capacitance (c l ) 0 100 200 300 400 0 50 100 150 200 c l (pf) t phl (ns) lv dd = 2.0v v l = 1.0v t a = 25 c xflobst xflobmt figure a2-97 output delay time (t plh ) vs. output load capacitance (c l ) 0 100 200 300 400 0 50 100 150 200 c l (pf) t phl (ns) lv dd = 2.0v v l = 1.0v t a = 25 c xflobmt xflobst figure a2-98 output delay time (t phl ) vs. output load capacitance (c l ) 0 5 10 15 20 0 50 100 150 200 c l (pf) t phl (ns) lv dd = 2.0v v l = 1.0v t a = 25 c xflob2t xflob3t xflob1t figure a2-99 output delay time (t plh ) vs. output load capacitance (c l ) 0 5 10 15 20 0 50 100 150 200 c l (pf) t phl (ns) lv dd = 2.0v v l = 1.0v t a = 25 c xflob2t xflob3t xflob1t figure a2-100 output delay time (t phl ) vs. output load capacitance (c l ) appendix a2 electrical characteristics data (xf type) embedded array S1X60000 series epson 335 design guide (5) output buffer rising/falling time vs. output load capacitance (c l ) 0 200 400 600 800 0 50 100 150 200 c l (pf) t r (0%-90%) (ns) lv dd = 2.0v v l = 1.0v t a = 25 c xflobmt xflobst figure a2-101 rising time (t r ) vs. output load capacitance (c l ) 0 200 400 600 800 0 100 150 200 c l (pf) t f (0%-90%) (ns) lv dd = 2.0v v l = 1.0v t a = 25 c xflobmt xflobst 50 figure a2-102 falling time (t f ) vs. output load capacitance (c l ) 0 0 20 30 40 0 50 100 150 200 c l (pf) t r (0%-90%) (ns) lv dd = 2.0v v l = 1.0v t a = 25 c xflob2t xflob3t xflob1t figure a2-103 rising time (t r ) vs. output load capacitance (c l ) 0 0 20 30 40 0 50 100 150 200 c l (pf) t f (0%-90%) (ns) lv dd = 2.0v v l = 1.0v t a = 25 c xflob2t xflob3t xflob1t figure a2-104 falling time (t f ) vs. output load capacitance (c l ) appendix a2 electrical characteristics data (xf type) 336 epson embedded array S1X60000 series design guide (6) pull-up and pull-down resistance z pull-up characteristics 1.6 lv dd (v) r plu (k ? ) 1.8 2.0 2.2 2.4 t a = 25 c type 1 type 2 250 200 150 100 50 0 figure a2-105 pull-up resistance (r plu ) vs. lv dd -60 -40 -20 0 20 40 60 80 100 120 140 t a ( c) r plu (k ? ) type 1 type 2 200 150 100 50 0 lv dd = 2.0v figure a2-106 pulll-up resistance (r plu ) vs. ambient temperature z pull-down characteristics 1.6 lv dd (v) r pld (k ? ) 1.8 2 2.2 2.4 t a = 25 c type 1 type 2 250 200 150 100 50 0 figure a2-107 pull-down resistance (r pld ) vs. lv dd -60 -40 -20 0 20 40 60 80 100 120 140 t a ( c) r pld (k ? ) type 1 type 2 200 150 100 50 0 lv dd = 2.0v figure a2-108 pulll-down resistance (r pld ) vs. ambient temperature appendix a2 electrical characteristics data (xf type) embedded array S1X60000 series epson 337 design guide (7) output waveforms z high speed type output buffer conditions: lv dd = 2.0v, t a = 25 c, c l = 15pf, i ol = 3 ma 3 2.5 2 1.5 1 0.5 0 -0.5 -1 output voltage v o (v) (5 ns/div) figure a2-109 output waveform (xflob3at) z normal type output buffer conditions: lv dd = 2.0v, t a = 25 c, c l = 15pf, i ol = 3 ma 3 2.5 2 1.5 1 0.5 0 -0.5 -1 output voltage v o (v) (5 ns/div) figure a2-110 output waveform (xflob3t) z low noise type output buffer conditions: lv dd = 2.0v, t a = 25 c, c l = 15pf, i ol = 3 ma 3 2.5 2 1.5 1 0.5 0 -0.5 -1 output voltage v o (v) (5 ns/div) figure a2-111 output waveform (xflob3bt) appendix a2 electrical characteristics data (xf type) 338 epson embedded array S1X60000 series design guide a2.4 characteristics of input/output buffers (5 v tolerant fail-safe cell) a2.4.1 input buffer characteristics (3.3 v 0.3 v) the input buffers comprised of 5 v tolerant fail-safe cells of the S1X60000 series exhibit the same characteristics as normal input buffers. therefore, see appendix 2.1.1, ?input buffer characteristics (3.3 v 0.3 v).? a2.4.2 input through current (3.3 v 0.3 v) the input buffers comprised of 5 v tolerant fail-safe cells of the S1X60000 series exhibit the same characteristics as normal input buffers. therefore, see appendix 2.1.2, ?input through current (3.3 v 0.3 v).? appendix a2 electrical characteristics data (xf type) embedded array S1X60000 series epson 339 design guide a2.4.3 output buffer characteristics (3.3 v 0.3 v) the 5 v tolerant fail-safe cells of the S1X60000 series include a control circuit (like the one shown in figure a2-112) to enable 5 v interfacing. therefore, note that the i ol and i oh characteristics of these cells differ from those of normal cells. tolerant fail-safe control hv dd pad figure a2-112 output buffer structure of 5 v tolerant fail-safe cell -100 -80 -60 -40 -20 0 -3.0 -2.0 -1.0 0.0 v oh -hv dd (v) i oh (ma) 5 v tolerant fail-safe normal v oh -i oh normal vs 5 v tolerant fail-safe (type 3b) figure a2-113 comparison between 5 v tolerant fail-safe cells and normal cells (1) list of output buffer specifications table a2-4 output current characteristics output current type number i oh *1 i ol *2 unit type 1 -3 3 ma type 2 -6 6 ma type 3 -12 12 ma note *1: v oh = hv dd - 1.0 v (hv dd = 3.3 v) *2: v ol = 0.4 v (hv dd = 3.3 v) appendix a2 electrical characteristics data (xf type) 340 epson embedded array S1X60000 series design guide (2) i ol -v ol and i oh -v oh z i ol -v ol type 1 0.0 10.0 20.0 30.0 40.0 50.0 0.0 1.0 2.0 3.0 4.0 v ol (v) i ol (ma) t a = 25 c hv dd = 3.0v hv dd = 3.3v hv dd = 3.6v figure a2-114 type 2 0.0 20.0 40.0 60.0 80.0 0.0 1.0 2.0 3.0 4.0 v ol (v) i ol (ma) t a = 25 c hv dd = 3.0v hv dd = 3.3v hv dd = 3.6v figure a2-115 type 3 0.0 50.0 100.0 150.0 0.0 1.0 2.0 3.0 4.0 v ol (v) i ol (ma) t a = 25 c hv dd = 3.0v hv dd = 3.3v hv dd = 3.6v figure a2-116 type 1 to 3 0.0 50.0 100.0 150.0 0.0 1.0 2.0 3.0 4.0 v ol (v) i ol (ma) type 2 type 3 type 1 t a = 25 c hv dd = 3.3v figure a2-117 appendix a2 electrical characteristics data (xf type) embedded array S1X60000 series epson 341 design guide z i oh -v oh type 1 -50.0 -40.0 -30.0 -20.0 -10.0 0.0 -4.0 -3.0 -2.0 -1.0 0.0 v oh - hv dd (v) i oh (ma) t a = 25 c hv dd = 3.0v hv dd = 3.3v hv dd = 3.6v figure a2-118 type 2 -100.0 -80.0 -60.0 -40.0 -20.0 0.0 -4.0 -3.0 -2.0 -1.0 0.0 v oh - hv dd (v) i oh (ma) t a = 25 c hv dd = 3.3v hv dd = 3.6v hv dd = 3.3v figure a2-119 type 3 -200.0 -150.0 -100.0 -50.0 0.0 -4.0 -3.0 -2.0 -1.0 0.0 v oh - hv dd (v) i oh (ma) t a = 25 c hv dd = 3.0v hv dd = 3.3v hv dd = 3.6v figure a2-120 type 1 to 3 -200.0 -150.0 -100.0 -50.0 0.0 -4.0 -3.0 -2.0 -1.0 0.0 v oh - hv dd (v) i oh (ma) t a = 25 c hv dd = 3.3v type 2 type 3 type 1 figure a2-121 appendix a2 electrical characteristics data (xf type) 342 epson embedded array S1X60000 series design guide (3) i ol and i oh temperature characteristics because the temperature characteristics of i ol and i oh are the same as those of output buffers comprised of normal cells, see (3) temperature characteristics of i ol and i oh in appendix 2.1.3, ?output buffer characteristics (3.3 v 0.3 v).? (4) output delay time vs. output load capacitance (c l ) 0 5 10 15 20 0 50 100 150 200 c l (pf) t plh (ns) hv dd = 3.3v v l = 1.65v t a = 25 c xfhobf2t xfhobf3at xfhobf1 figure a2-122 output delay time (t plh ) vs. output load capacitance (c l ) 0 5 10 15 20 0 50 100 150 200 c l (pf) t phl (ns) hv dd = 3.3v v l = 1.65v t a = 25 c xfhobf2t xfhobf3a xfhobf1t figure a2-123 output delay time (t phl ) vs. output load capacitance (c l ) appendix a2 electrical characteristics data (xf type) embedded array S1X60000 series epson 343 design guide (5) output buffer rising/falling time vs. output load capacitance (c l ) the 5 v tolerant fail-safe cells of the S1X60000 series include a control circuit (like the one shown in figure a2-124) to enable 5 v interfacing. therefore, note that the t r and t f characteristics of these cells differ from those of normal cells. 0 1 2 3 x60k normal buffer vs. 5v tolerant buffer (type1 hv dd = 3.3v lv dd = 2.5v c = 15pf) time (lin) (time) time (lin) (time) voltages (lin) 200n 180n 160n 140n 120n 100n 80n 60n 40n 20n 0 0 1 2 3 x60k normal buffer vs. 5v tolerant buffer (type2 hv dd = 3.3v lv dd = 2.5v c = 15pf) voltages (lin) 200n 180n 160n 140n 120n 100n 80n 60n 40n 20n 0 time (lin) (time) 0 1 2 3 x60k normal buffer vs. 5v tolerant buffer (type3 hv dd = 3.3v lv dd = 2.5v c = 15pf) voltages (lin) 200n 180n 160n 140n 120n 100n 80n 60n 40n 20n 0 figure a2-124 comparison between 5 v tolerant fail-safe cells and normal cells appendix a2 electrical characteristics data (xf type) 344 epson embedded array S1X60000 series design guide 0 10 20 30 40 0 50 100 150 200 c l (pf) t r (10%-80%) (ns) hv dd = 3.3v v l = 1.65v t a = 25 c xfhobf2t xfhob3at xfhobf1t figure a2-125 rising time (t r ) vs. output load capacitance (c l ) 0 10 20 30 40 0 50 100 150 200 c l (pf) t f (10%-80%) (ns) hv dd = 3.3v v l = 1.65v t a = 25 c xfhobf2t xfhob3at xfhobf1t figure a2-126 falling time (t f ) vs. output load capacitance (c l ) (6) pull-up and pull-down characteristics because the pull-up/pull-down characteristics are the same as those of output buffers comprised of normal cells, see (6) pull-up/pull-down characteristics in appendix 2.1.3, ?output buffer characteristics (3.3 v 0.3 v).? appendix a2 electrical characteristics data (xf type) embedded array S1X60000 series epson 345 design guide (7) output waveforms z high speed 0 1 2 3 6 5.5 4.5 3.5 2.5 1.5 500m 500m 1 2 3 2.5 1.5 5 4 high speed type: hv dd = 3.3v, t a = 25c, c l = 15pf, i ol = 12ma) time (lin) (time) voltages (lin) 80n 75n 70n 60n 50n 65n 55n 45n 35n 30n 40n 20n 25n 15n 10n 5n 0 figure a2-127 output waveform (xfhobf3at) z low noise 0 1 2 3 6 5.5 4.5 3.5 2.5 1.5 500m 500m 1 2 3 2.5 1.5 5 4 low noise type: hv dd = 3.3v, t a = 25c, c l = 15pf, i ol = 12ma) time (lin) (time) voltages (lin) 80n 75n 70n 60n 50n 65n 55n 45n 35n 30n 40n 20n 25n 15n 10n 5n 0 figure a2-128 output waveform (xfhobf3bt) appendix a2 electrical characteristics data (xf type) 346 epson embedded array S1X60000 series design guide (8) output waveforms (3.3 v interface) the waveforms shown in figures a2-130, a2-131, and a2-132 show output waveforms under the conditions in figure a2-129. v pu r pu c l v pu = 3.3v r pu = 0.5,1,2,5 ? c l = 15pf hv dd /lv dd = 3.3v/2.5v figure a2-129 evaluation circuit z type 1 0 1 2 3 4 0 20 40 60 80 100 120 140 160 180 200 time (ns) output (v) r = 0.5 (k ? ) r = 1.0 (k ? ) r = 2.0 (k ? ) r = 5.0 (k ? ) input waveform without pull-up resistors figure a2-130 output waveforms (xfhobf1t) z type 2 0 1 2 3 4 0 20 40 60 80 100 120 140 160 180 200 time (ns) output (v) r = 0.5 (k ? ) r = 1.0 (k ? ) r = 2.0 (k ? ) r = 5.0 (k ? ) input waveform without pull-up resistors figure a2-131 output waveforms (xfhobf2t) z type 3 0 1 2 3 4 0 20 40 60 80 100 120 140 160 180 200 time (ns) output (v) r = 0.5 (k ? ) r = 1.0 (k ? ) r = 2.0 (k ? ) r = 5.0 (k ? ) input waveform without pull-up resistors figure a2-132 output waveforms (xfhobf3at) appendix a2 electrical characteristics data (xf type) embedded array S1X60000 series epson 347 design guide (9) output waveforms (5 v interface) the waveforms shown in figures a2-134, a2-135, and a2-136 show output waveforms under the conditions in figure a2-133. v pu r pu c l v pu = 5.5v r pu = 0.5,1,2,5 ? c l = 15pf hv dd /lv dd = 3.0v/2.3v figure a2-133 evaluation circuit z type 1 0 1 2 3 4 5 6 0 20 40 60 80 100 120 140 160 180 200 time (ns) output (v) r = 0.5 (k ? ) r = 1.0 (k ? ) r = 2.0 (k ? ) r = 5.0 (k ? ) input waveform without pull-up resistors figure a2-134 output waveforms (xfhobf1t) z type 2 0 1 2 3 4 5 6 0 20 40 60 80 100 120 140 160 180 200 time (ns) output (v) r = 0.5 (k ? ) r = 1.0 (k ? ) r = 2.0 (k ? ) r = 5.0 (k ? ) input waveform without pull-up resistors figure a2-135 output waveforms (xfhobf2t) z type 3 0 1 2 3 4 5 6 0 20 40 60 80 100 120 140 160 180 200 time (ns) output (v) r = 0.5 (k ? ) r = 1.0 (k ? ) r = 2.0 (k ? ) r = 5.0 (k ? ) input waveform without pull-up resistors figure a2-136 output waveforms (xfhobf3at) international sales operations america epson electronics america, inc. - headquarters - 150 river oaks parkway san jose, ca 95134, u.s.a. phone: +1-800-228-3964 fax: +1-408-922-0238 - sales offices - west 1960 e. grand avenue flr2 ei segundo, ca 90245, u.s.a. phone: +1-800-249-7730 fax: +1-310-955-5400 central 101 virginia street, suite 290 crystal lake, il 60014, u.s.a. phone: +1-800-853-3588 fax: +1-815-455-7633 northeast 301 edgewater place, suite 210 wake?ld, ma 01880, u.s.a. phone: +1-800-922-7667 fax: +1-781-246-5443 southeast 3010 royal blvd. south, suite 170 alpharetta, ga 30005, u.s.a. phone: +1-877-332-0020 fax: +1-770-777-2637 - design support centers - san jose asic design center 150 river oaks parkway san jose, ca 95134, u.s.a. phone: +1-408-922-0200 fax: +1-408-922-0238 europe epson europe electronics gmbh - headquarters - riesstrasse 15 80992 munich, germany phone: +49-89-14005-0 fax: +49-89-14005-110 d?sseldorf branch office altstadtstrasse 176 51379 leverkusen, germany phone: +49-2171-5045-0 fax: +49-2171-5045-10 french branch office 1 avenue de l atlantique, lp 915 les conquerants z.a. de courtaboeuf 2, f-91976 les ulis cedex, france phone: +33-1-64862350 fax: +33-1-64862355 barcelona branch office barcelona design center edi?io testa, c/alcaide barnils 64-68, modulo c 2a planta e-08190 sant cugat del vall?s, spain phone: +34-93-544-2490 fax: +34-93-544-2491 uk & ireland branch office 8 the square, stockley park, uxbridge middix ub11 1fw, united kingdom phone: +44-1295-750-216/+44-1342-824451 fax: +44-89-14005 446/447 scotland design center integration house, the alba campus livingston west lothian, eh54 7eg, scotland phone: +44-1506-605040 fax: +44-1506-605041 asia epson (china) co., ltd. 23f, beijing silver tower 2# north rd dongsanhuan chaoyang district, beijing, china phone: +86-10-6410-6655 fax: +86-10-6410-7320 shanghai branch 7f, high-tech bldg., 900, yishan road, shanghai 200233, china phone: +86-21-5423-5522 fax: +86-21-5423-5512 epson hong kong ltd. 20/f., harbour centre, 25 harbour road wanchai, hong kong phone: +852-2585-4600 fax: +852-2827-4346 telex: 65542 epsco hx epson taiwan technology & trading ltd. 14f, no. 7, song ren road, taipei 110 phone: +886-2-8786-6688 fax: +886-2-8786-6677 hsinchu office no.99, jiangong road, hsinchu city 300 phone: +886-3-573-9900 fax: +886-3-573-9169 epson singapore pte., ltd. 401 commonwealth drive, #07-01 haw par technocentre, singapore 149598 phone: +65-6586-3100 fax: +65-6472-4291 seiko epson corporation korea office 50f, kli 63 bldg., 60 yoido-dong youngdeungpo-ku, seoul, 150-763, korea phone: +82-2-784-6027 fax: +82-2-767-3677 gumi office 6f, good morning securities bldg. 56 songjeong-dong, gumi-city, 730-090, korea phone: +82-54-454-6027 fax: +82-54-454-6093 seiko epson corporation electronic devices marketing division ed international marketing department 421-8, hino, hino-shi, tokyo 191-8501, japan phone: +81-42-587-5814 fax: +81-42-587-5117 S1X60000 series design guide design guide S1X60000 series design guide embedded array S1X60000 series epson electronic devices website electronic devices marketing division http://www.epsondevice.com document code: 404624401 first issue september, 2004 printed in japan c b this manual was made with recycle papaer, and printed using soy-based inks. |
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